Several suggestions on EMC design of single chip microcomputer

The operating frequency of the microcontroller The design of the microcontroller should choose a lower operating frequency according to the needs of the customer. First, let me introduce the advantages of doing so: using a low crystal oscillator and bus frequency allows us to choose a smaller microcontroller to meet the timing requirements, so that the operating current of the microcontroller can become lower, and most importantly, the current peak from VDD to VSS will be smaller.

Of course, we need to make a compromise here, because the customer's requirements may be compatible and platform-based (the current development trend of automotive electronics is platformization). Choosing a higher operating frequency can be compatible with more platforms and is also convenient for future upgrades and expansions. Therefore, a lower acceptable operating frequency should be selected.

Appropriate output drive capability Given the load specification, rise and fall time, choosing the appropriate output rise time, and minimizing the peak current of the output and internal driver are one of the most important design considerations for reducing EMI. Unmatched drive capability or failure to control the output voltage change rate may result in impedance mismatch, faster switching edges, overshoot and undershoot of the output signal, or power supply and ground bounce noise.

To design the output driver of the microcontroller, first determine the load required by the module, the rise and fall time, and the output current (to be continued). Based on the above information, the driving capacity and the voltage slew rate are controlled. Only in this way can the module requirements and EMC requirements be met.

When the driver capacity is higher than the actual charging speed required by the load, a higher edge rate will be generated, which will have two disadvantages. The harmonic components of the signal are increased. Together with the load capacitance and parasitic internal bonding lines, IC packaging, and PCB inductance, it will cause the signal to overshoot and undershoot.

Selecting the appropriate di/dt switching characteristics can be achieved by carefully selecting the size of the driving capacity and controlling the voltage slew rate. The best option is to use a constant voltage slew rate output buffer that is independent of the load. The voltage slew rate of the same pre-driver output can be reduced (that is, the rise and fall time can be increased), but the corresponding propagation delay will increase, and we need to control the total switching time).

Use the driving capacity of the programmable output port of the microcontroller to meet the actual load requirements of the module.

The simplest driver of the programmable output port is a pair of drivers in parallel. Their MOS Rdson is different and the output current capacity is also different. We can choose different modes during testing and actual use. In fact, the current microcontrollers generally have at least two modes to choose from, and some even have three (strong, medium, and weak). When there is enough margin in the timing constraints, the edge of the internal clock drive is slowed down by reducing the output capacity.

To reduce the peak current and di/dt of the synchronous switch, an important consideration is to reduce the capacity of the internal clock drive (in fact, it is the amplification factor, and the penetration current is greatly related to it). Reducing the current on the clock edge will significantly improve EMI. Of course, the disadvantage of doing so is that the average current of the microcontroller may increase due to the longer turn-on time of the clock and load. A compromise needs to be made between fast edges and relatively high peak currents, and current pulses with longer times and slower edges.

It is best not to exceed the actual demand for the internal drive (inverter) of the crystal oscillator.

This problem has actually been discussed before. When the gain is too large, it will cause greater interference.

Design the driver clock with minimum through-current. The bus and output driver should minimize the traditional current through-current [overlap current, short-circuit current] as much as possible. It is the current from the power supply to the ground when the PMOS and NMOS are turned on at the same time during the switching process of the microcontroller. The through-current directly affects EMI and power consumption.

This content is actually inside the microcontroller, the clock, bus and output driver. The way to eliminate or reduce the through-current is to try to turn off one FET first and then turn on another FET. When the current is large, additional pre-drive circuits or voltage slew rates are required.