Teach you how to understand FET and choose the right device

Nowadays, FET can be found in almost every power supply. Almost every power supply engineer has used it, either for inversion, rectification or just as a switch.

Due to different uses, each manufacturer has made special optimizations for FETs for different uses, resulting in multiple models of FETs with the same withstand voltage/current. Naturally, each manufacturer has its own unique characteristics. There are many types of FETs, high and low.

It can be seen that as an engineer, it is very important to understand FET and select the most suitable device!

FET is a large-scale integrated power switch composed of a large number of small FETs connected in parallel on a silicon chip. Each small FET is called a cell, and the current of each cell is not large, only in the hundreds of milliamperes. Designers use the method of ants defending a tree; a large number of FETs are connected in parallel to achieve a large switching current. That is, under the same size of silicon chip and withstand voltage, the more cells, the greater the allowable current.

In FET, not only are the FET cells connected in parallel, but many parasitic diodes are also connected in parallel!

When used in situations where overvoltage is serious, you must pay attention to this! Large avalanche tolerance; can improve system reliability!

The capability and voltage of FET will never change throughout life!

The principle structure of each cell is shown in the figure

The red color indicates the channel of the FET switch, and the blue color indicates the parasitic body diode.

Normally, FET is off. When a positive voltage is applied to the gate, many electrons are attracted near the gate. In this way, the adjacent P-type semiconductor becomes N-type, forming a channel (N channel) connecting two N transistors, and FET is turned on. Obviously, the higher the withstand voltage of FET, the longer the channel, and the greater the resistance. This is why the RDSON of high-voltage FET is large.

Conversely, the same is true for P-channel FET, which will not be described here.

Therefore, power FET is often equivalent to:

[page]

Field Effect Transistor (FET) is short for field effect tube. Most carriers participate in the conduction, also known as unipolar transistor. It is a voltage-controlled semiconductor device. It has three polarities, gate, drain, and source. Its characteristic is that the internal resistance of the gate is extremely high. The silicon dioxide material can reach hundreds of megohms. It is a voltage-controlled device. It has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and wide safe working area. It has become a strong competitor of bipolar transistors and power transistors.

According to the structure, field effect tubes are divided into two categories: junction field effect (JFET for short) and insulated gate field effect (MOSFET for short).

According to the channel material: junction type and insulated gate type are divided into N channel and P channel.

According to the conduction mode: depletion type and enhancement type, junction field effect transistors are all depletion type, and insulated gate field effect transistors have both depletion type and enhancement type.

Field effect transistors can be divided into junction field effect transistors and MOS field effect transistors, and MOS field effect transistors can be divided into four categories: N-channel depletion type and enhancement type; P-channel depletion type and enhancement type.

The main parameters of field effect tube

Idss — Saturation drain-source current. It refers to the drain-source current when the gate voltage UGS=0 in a junction or depletion-type insulated gate field effect transistor.

Up — Pinch-off voltage. It refers to the gate voltage when the drain-source is just cut off in a junction or depletion-type insulated gate field effect transistor.

Ut — Turn-on voltage. It refers to the gate voltage when the drain and source are just turned on in the enhanced insulated gate field effect tube.

gM — transconductance. It indicates the control ability of the gate-source voltage UGS over the drain current ID, that is, the ratio of the change in the drain current ID to the change in the gate-source voltage UGS. gM is an important parameter to measure the amplification ability of the field effect tube.

BVDS — Drain-source breakdown voltage. It refers to the maximum drain-source voltage that the field effect tube can withstand for normal operation when the gate-source voltage UGS is constant. This is a limit parameter, and the operating voltage applied to the field effect tube must be less than BVDS.

PDSM — Maximum dissipation power, also a limit parameter, refers to the maximum drain-source dissipation power allowed when the performance of the field effect tube does not deteriorate. When used, the actual power consumption of the field effect tube should be less than PDSM and leave a certain margin.

IDSM — Maximum drain-source current. It is a limit parameter, which refers to the maximum current allowed to pass between the drain and the source when the field effect tube is working normally. The working current of the field effect tube should not exceed IDSM

Field effect tubes are voltage-controlled components, while transistors are current-controlled components. When only a small amount of current is allowed to be taken from the signal source, field effect tubes should be used; when the signal voltage is low and more current is allowed to be taken from the signal source, transistors should be used.

Field effect tubes use majority carriers to conduct electricity, so they are called unipolar devices, while transistors have both majority carriers and minority carriers to conduct electricity, so they are called bipolar devices.

The source and drain of some field effect tubes can be used interchangeably, and the gate voltage can be positive or negative, which is more flexible than transistors.

Field effect tubes can work under very low current and very low voltage conditions, and its manufacturing process can easily integrate many field effect tubes on a silicon wafer, so field effect tubes have been widely used in large-scale integrated circuits.

FET is made of real materials; there are conductors/semiconductors/insulators inside. The combination of these materials makes FET. So, any two insulated conductors naturally form a physical capacitor - parasitic capacitance.

The red one is the parasitic capacitance Coss between DS, the blue one is the Miller capacitance Cgd, and the black one is the gate-source capacitance Cgs.

Cgd+Cgs=Ciss——input capacitance

Coss——output capacitance

Therefore, Cgd/Cds exists in theory and is listed in the data sheet. It can also be used as a parameter in the micro-variable equivalent analysis, but it is only used in the micro-variable equivalent analysis in linear amplification. In the engineering analysis of the switching process, the abnormal change leads to the fact that only the charge value can be used to measure it.

Qgd is the charge stored in Cdg (Maitreya charge), and Qds is the charge stored in Cds.

Next, we analyze how these charges affect the operation of FET in the on/off state.

When the FET is statically turned off, the Cgd/Cgs charging status is as shown in the figure:

The gate voltage is zero, Qgs = 0. Qgd is fully charged, Vgd = Vds.

Note: Since Cds is usually connected in parallel with other stray capacitances and affects the power supply together, it will not be analyzed here for the time being. The problem will be discussed together with stray parameters later.

Apply a positive pulse to the gate of the FET.

Since Cgd has a very small capacitance when it is subjected to positive voltage (although Cgd is small, Qgd=Cgd*Ugd, Qgd is still very large), Cgs is much larger than Cgd. Therefore, at the beginning of the pulse, the driving pulse mainly charges Cgs until the FET starts to turn on. When turned on, the gate voltage of the FET is the threshold voltage Vth.

In most cases, only a small current flows through the FET before the gate voltage reaches Vth. The FET is always in the off state.

When the FET gate voltage reaches Vth, the FET begins to conduct. Regardless of whether the load is at the drain or the source, it will bear part or all of the voltage due to the current flowing through it. In this way, the FET will go through a process from bearing all the voltage in the blocking state to a short circuit with almost no voltage drop.

During this process, Cgd undergoes a discharge process synchronously, and the discharge current is I=Qgd/ton.

Igd——Miller current shunts the drive current of FET, making the gate voltage of FET rise slowly.

The larger the Maitreya charge; the longer this slope is.

The Maitreya charge is not only related to the device but also to the drain voltage. Generally, the higher the voltage, the greater the charge.

When the gate voltage of FET reaches Vth, current flows through the channel of FET. At this time, FET works in the linear region. The apparent slope of FET changes with the change of Id. However, from the change of Vg and Id, the ratio of the two is the FET crossing S. That is, S=(Id2-Id1)/(Vgs2-Vgs1).

Among them, the bright lines of the same thickness are grouped together, representing the relationship between their respective Vg and Id.

Since the gate voltage slows down during the FET opening process, it is caused by the shunt of the Maitreya capacitor, so it is also called the Maitreya effect region.

Therefore, in the intermittent flyback power supply, the gate voltage slope of the Maitreya effect region remains basically unchanged, while the slope of the forward, half/full bridge, etc. varies with the load.

Maitreya effect time (switching time) ton/off = Qgd/Ig

Note: 1) Ig refers to the gate drive current of FET.

FET “ON”      Ig=（Vb-Vth）/Rg

2) Vb: Steady-state gate drive voltage

After passing through the Maitreya region, the FET is fully turned on. The PN junction that originally blocked the DS is short-circuited by the opened channel. Due to the loss of part of the insulating layer, Cgd becomes larger and is equivalent to Cgs. In addition, Cgd is physically connected in parallel with Cgs through the low-impedance open channel. In this way, the later driving gate voltage edge changes. As shown in the figure:

The physical changes during the FET's turn-off and turn-on processes are the same, but the process is just the opposite.

Analyze it yourself! Let us share your results!

As mentioned earlier, the driving waveform of a complete cycle is shown in the figure:

Here is a typical measured grid & VD waveform for you to experience the mystery.

[page]

Take a closer look at the FET channel structure and see if you can piece it together like this:

Such as ZVS/synchronous rectification. The reverse recovery time and charge amount determine the efficiency and electromagnetic noise of the power supply.

Look at trr and Qrr

trr is the diode recovery time; Qrr is the recovery charge. In the circuit, it is similar to the parallel capacitor between the DS of the FET. The larger these two values ​​are, the larger the capacitance is. This capacitance value is also related to the temperature and the actual current flowing through the diode. The larger the current is and the higher the temperature is, the larger the equivalent capacitance is.

Therefore, when comparing different data sheets, you must clearly understand the test conditions. Otherwise, inferior tubes can also be marked with good parameters.

Here, the time the current flows through the diode has basically nothing to do with Qrr&trr.

The two quantities AR/EAS describe the ability of FET to resist avalanche breakdown.

EAR describes the repeatable avalanche withstand. EAS describes the single-shot withstand.

For example, in a low-power flyback, after the RCD absorption is removed, the drain voltage under high current load needs the EAR to assess safety. Another example is in a high-current half/full bridge circuit, when the bridge is short-circuited, the current is very large; even if the FET can be turned off in the safe working area, overvoltage will still be generated due to the effect of stray parasitic inductance such as the lead wire. When it is turned off quickly, the overvoltage will exceed the FET withstand voltage limit and break down. EAS is a parameter to measure whether the FET is safe at this time... Here are only two examples of the concepts of these two quantities and two practical engineering applications. Their significance is far more than this.

Here is a typical graph of these two quantities:

Secure Operating Area SOA

Look at these two pictures first:

These are two 600V MOSFETs, both of which can withstand the maximum saturation current at 600V. That is, at a gate voltage of 15V, the maximum current that the MOSFET can flow through (MOSFET enters the linear region; it is in a constant current state), and the current at this time does not increase with the increase of voltage!

The status position is shown in the red area in the blue circle in the figure (up to 600V, some are exaggerated):

Obviously, both FETs can withstand this voltage and current, but the duration of their operation is different. The left picture shows that it can withstand 1 microsecond, while the right picture can withstand about 10 microseconds. (Reprinted from Power Network)