Flat panel display controller AL300 and its application TheapplicationoftheFlatPanelDisplayMonitorControllerAL300

      Abstract: The flat panel display controller AL300 is produced by AVERLogic Company and can be used to control and connect PC or video sources with flat panel displays (such as LCD, PDP, etc.). The article introduces the characteristics, functions, principles and application of the chip in flat display systems. And combined with the application circuit, the software flow is given.

    Keywords: flat panel display; controller; OSD (on-screen display); phase-locked loop; bus; AL300

    1 Overview

    Flat panel displays (FPD) include liquid crystal displays (LCD) and plasma displays (POP). Typically, flat panel displays only support progressive scan format data input, and the resolution is fixed. The flat panel display controller AL300 can be used to convert video/graphic digital signals of different formats and resolutions into data formats that can be displayed by flat panel displays. Its typical application is shown in Figure 1.

    In the figure, the TV decoder can be SAA7111A from PHILIPS or KS0127 from SAMSUNG. Both decoders can automatically identify the format of the input video signal, and then decode and output 24bit RGB or 16bit YUV digital signals, while outputting Hsync, Vsync, Blank and sampling clock.

   Analog R, G, B graphics signals from PC are input to AL300 via AL875. AL875 is a product of AVERLogic Company. It is packaged in 100 pin 14×20mm PQFP. It is a three-channel 8bit A/D converter that can digitize R, G, and B graphics signals of PC. The 110MHz slew rate supports graphics display resolutions up to 1280×1024 (64Hz). Its A/D conversion data is output in binary code. Output enable terminal () can switch the output state between high impedance and active for easy output control. The working status of the chip can be passed                Interface programming control.

  If PC digital graphics signals are input directly, the digital graphics signals can be input to AL300 through LVDS (Low Voltage Differential Signaling) DS90CF583/DS90CF584. DS90CF583 is a transmitter that can convert 24 bitRGB data into 4 sets of LVDS in one clock cycle; DS90CF584 is a receiver that can convert the received LVDS data stream into TTL/CMOS data. To facilitate high-speed and long-distance transmission of multiple digital signals. Its clock frequency is up to 65MHz and supports bandwidth up to 227Mbytes/s.

  2. Working principle of AL300

  If the input is a VCD/DVD signal, an MPGA decoder can be used to connect to the AL300.

  AL300 is a powerful new flat panel display control chip with a variety of control functions that can be implemented by a microprocessor through an interface. The power supply voltage is 3.3V, the I/O port is TTL level, and it adopts 160pin 28×28mm PQFP package. The schematic block diagram of AL300R is shown in Figure 2.

  2.1 Scan mode detection circuit

   AL300 has an input signal scanning mode detection function. It can detect the format of the input signal based on the input line and field scanning signals Hsync and Vsync. When the line speed of the input signal changes, it will generate an interrupt signal and send it to the microprocessor, and the microprocessor will perform mode setting and control.

  2.2 Input data format

  AL300 can receive four input data formats: 24bit RGB 8bit ITU-RBT656 (CCIR656 422), 16bitCCIR601 422 and 42bit CCIR601 444; the connection methods of TV decoders of various input data formats and AL300 are shown in Figure 3.

  As can be seen from Figure 3, the input video format is determined by the pin YUVin. When YUVin=1, the YUV input data is selected; when YUVin=0, the RGB input data is valid.

  2.3 Magnification function

  AL300 has independent horizontal and vertical amplification functions. The horizontal amplification coefficient is defined by the 1-bit register HRATIO. The high 3 bits determine the integer part and the low 8 bits determine the decimal part. The data of HRATIO is determined by the input image lattice and the enlarged display image lattice. The vertical amplification coefficient is defined by the 15-bit register VRA-TIO, of which the high 3 bits are the integer part and the low 12 bits are the decimal part. Its value is also determined by the input image size and the enlarged image size. The linear range of horizontal and vertical magnification is 1 to 8 times.

  2.4 On-screen display (OSD)

  The AL300 provides two independent On-Screen Display (OSD) windows to allow control menus, text or titles to be overlaid on the output display. Its OSD function is very flexible, and its font, size, and display position can all be programmed and controlled. The internal 1kB SRAM provides storage of OSD information. OSD can store word tables or bitmaps in internal SRAM or external expansion ROM. The OSD key can select the color of the bitmap superimposed on the screen, and the four selected OSD color data are sent to the logic operation unit through the flashing circuit. The logic operation unit can produce special effects such as transparent, opaque, negative, and background.

  2.5 output interface

  AL300 supports both single pixel/clock and dual pixel/clock display modes. Its output interface includes: 24bitRGB odd pixel data, 24bit RGB even pixel data, display enable, display clock, even pixel clock, odd pixel clock, horizontal synchronization and field synchronization and other signals. Its display mode can be passed                 Interface programming control.

  3. AL300 register description

  AL300 has a total of 124 internal control registers, throughInterface register programming can control AL300 to achieve various functions. The following is an introduction to register classification.

  3.1 Configuration register (00h~07h)

  It includes three read-only registers, which are used to record the company ID (46h), version number and chip serial number respectively; the other five are read-write registers, through which the working status of the chip can be set: such as input type (video or graphics), Synchronization signal (separate synchronization or composite synchronization), power-down mode, bypass mode, phase-locked loop working status, clock polarity or jitter control selection, etc.

  3.2 Output phase-locked loop and gain register (10h～1Bh)

  This register includes eight read-write registers, which are used to set the phase-locked loop parameters and the amplification coefficient and initial phase in the horizontal and vertical directions.

  3.3 Input clock register (20h~29h)

  It includes six read-write registers, which are used to set the horizontal effective starting position, horizontal effective size, vertical effective starting position and vertical effective end position of the input image.

  3.4 Output clock register (30h～3Ch)

  It includes ten read-write registers, which are respectively used to define the total number of horizontal pixels of the output display, the horizontal synchronization end position, the horizontal display start, the horizontal display end, the vertical synchronization end position, OSD flicker control, the vertical display start position, the vertical Shows end position, frame delay, etc.

  3.5 Interrupt and internal clock register (40h～43h)

  It includes four read-write registers. 40h is used to enable settings of three interrupt sources. These three interrupt sources are: line speed change, Vsync arrival, odd field arrival of input video; 41h and 42h are used to define the internal reference clock. The number of horizontal pixels and rows; 43h defines output control, including lookup table enable, dual-pixel output and output clock phase inversion.

  3.6 Input clock measurement register (60h~65h)

  Including four read-only registers, 60h records the input status (polarity of the input synchronization signal, whether the input is an odd field or an even field, whether the video input is in the valid area, etc.); 61h, 62h records the input line speed; 63h, 64h records the input vertical Total number of lines; 65h indicates the status of three interrupt sources.

  3.7OSD control register (80h～BBh)

  It includes 43 read-write registers, through which the OSD mode, the four colors used by the OSD, and the respective parameters of the two OSD windows can be defined.

     4. Application of AL300 in flat panel display system

    Figure 4 is the hardware circuit structure diagram of AL300 applied in LCD flat panel display system.

    In the figure, SAA7111A is selected as the TV decoder to receive PAL/NTSC/SECAM three-standard video signals; AL875 is a three-channel 8bit A/D converter used to digitize the R, G, and B graphics signals of the PC; SMJ27C512 is EPROM with a storage byte of 64k is used to store OSD fonts and bitmaps. TVCLK, TVHS, TVVS and TVREF of AL300 are the horizontal and vertical synchronization and sampling clock of the input video signal; GHS, GVS and GCLK are the horizontal and vertical synchronization and sampling clock of the input graphics signal; YUVI is the input format selection. When YUVin=1, the input The format is YUV, and when YU-Viv=0, the input format is RGB; RIN/YIN[7:0] is the input R data or Y data, GIN/UVIN[7:0] is the input G data or UV data; BIN is the input B data; ROMDA-TA[7:0] is the 8-bit data of the font ROM, ROMADDR[15:0] is the 16-bit address; IRQ and HOSTCLK are the interrupt requests and clocks sent to the microcontroller; PSDPEN is the display enable; PCLKE, PCLKO, SCLK, PHS, and PVS are the clock and horizontal and vertical synchronization of the output video signal; RE[7:0], GE[7:0], BE[7:0] are in single-pixel mode The following is the R, G, and B data of the output video signal. In dual-pixel mode, it is the even pixel R, G, and B data of the output video signal; RO[7:0], GO[7:0], BO[ 7:0] is the odd pixel R, G, B data of the output video signal in dual-pixel mode; SDA and SCL arecontrol interface.

    5. System software design

    The program flow of the software in the LCD flat panel display system is shown in Figure 5 .