Wiring considerations for non-isolated DC-DC converters

    Abstract: Integrated DC-DC power controllers have emerged over the years offering increasingly better performance. It frees product designers from the heavy power supply design and relieves a lot of pressure. However, it also makes many engineers become more and more careless about the design of system power supply circuits. It is worth noting that power supply design is still a key part of system design. , especially the design of switching converters requires more attention. This article mainly discusses the circuit board wiring rules when designing a non-isolated DC-DC converter.

    Keywords: Power supply DC-DC converter EMI

The first rule for optimizing wiring is to isolate the converter. The DC-DC converter is a strong source of electromagnetic field interference. Usually its EMI spectrum range extends from the switching frequency to more than 100MHz. In order to reduce capacitive coupling and magnetic field loop coupling, the converter must be located away from other circuits, especially small-signal analog circuits. Isolating a converter is not always an easy task. There are some boards where the input voltage is on one side of the converter and the output voltage is distributed to the other side of the converter. For example, VME boards or telecom circuit boards with current Very complex traces up to 20A, which use a single connector to bring in the input voltage and distribute several output voltages to the backplane. The most efficient way is to place the DC-DC converter close to the connector. location to reduce resistive voltage drops, however this area is densely populated with interface drivers, backplane buses, etc., with corresponding coupled noise. Adding a power connector to the board requires additional board area and cost.

The resistance of the copper wire is the most limiting factor. For a given length and thickness of copper wire, its resistance is:

R=ρ×(1/S)

In the formula: 1 is the length of the copper wire, in meters; S is the area of ​​the copper wire, in square meters: ρ is the resistivity of the material, and the resistivity of copper is 1.7×10 -8Ω/m@20℃, or 2.1×10 -8Ω/m@70℃. For example: at 20°C, the resistance of a 0.5cm wide and 35μm thick copper wire is 1mΩ/cm. This value may be negligible in most cases, but when distributing a power supply with a voltage of 2.5V and a current of up to 10A between two upper continuators and the backplane, this parameter has to attract attention.

On some circuit boards, the thickness of the copper traces contains a layer of lead-tin alloy. The equivalent resistance of this layer is approximately twice that of copper.

Resistivity of copper =2.07×10 -7Ω/m

Resistivity of tin=1.14×10 -7Ω/m

Considering accuracy and line loss, the converter needs to be kept away from the connector. Remote sampling of VOUT close to the connector can effectively limit the drop, but be careful about capacitive coupling. To confine high currents to a designated area, all power cords should be connected to one end of the connector.

MOSFET driver

As the switching frequency increases, the switching times become shorter and shorter - for a converter with a switching frequency of 500kHz, the switching time is typically 10ns. At this frequency, even using the shortest lead will produce a large impedance. In order to ensure reasonable wiring of the MOSFET drive circuit, the schematic block diagram of the converter needs to be carefully analyzed.

Figure 1 shows the synchronous rectification and buck-type control used to power laptop computers. The energy from the energy storage capacitor (C6 and C7) drives the gate of the MOSFET through a resistance of several ohms to the output. Note: The gate drive of the high-side N-channel MOSFET (Q1) is in a floating state, and the N-channel driver works the same as the charge pump. Carefully considering the current path in Figure 1 when the MOSFET is turned on, it is easy to find that any equivalent series inductance will cause harm to the system. In some cases, the higher peak current will only increase the switching losses, while in other cases, it will cause the breakdown of both MSOFETs due to crosstalk (the power switches are turned on at the same time). Therefore, ideal traces between the following components should be short and wide: C6 and Vdd, C6 and Q2 (S), C7 and BST, C7 and LX, Q1 (G) and DH, Q2 (G) and DL, Q1 ( S) and LX, Q2 (S) and PGND. Note that the distributed inductance of 1cm of wiring is approximately 10nH.

C6 supplies power to Q1 and Q2, but not on the same circuit. It acts as a filter capacitor for Q1 and a storage capacitor for Q2. Because C6 cannot be mounted immediately next to both the high-side and low-side drivers, it is placed close to Vdd and PGND (where the peak current flows), and also close to the PGND, DL, and Vdd pins of C7.MAX1710 The close proximity is not accidental. The purpose of installing C6 close to Q2 is to reduce the length of the ground wire between PGND, C6 (I) and Q2 (S). Connect this ground wire to the ground plane at a single point near the PGND pin. To prevent common-mode impedance coupling, LX should be connected to Q1 and PGND/C6(A) to the source of Q2. When di/dt is large, each time hole will add tens of nH of inductance, and the number of vias should be limited as much as possible. Therefore, it is best to place all power components on the component layer, even for SMD devices.

In specific applications, the selected controller often has too much margin. For example, use a 10A controller to produce an output of 3A. For cost reasons, MOSFETs with the smallest margin are often selected, so the on-chip driver has excessive driving capability, resulting in excessive gate drive. Excessive or too fast gate drive will produce larger switching noise and RF interference, while smaller or slower gate drive will result in larger switching losses of MOSFETs and diodes. The compromise is to limit the slew rate of the waveform as much as possible to reduce EMI while maintaining acceptable conversion efficiency specifications.

Power stage wiring

In the switching converter, some nodes have higher di/dt, and some nodes have higher dv/dt. In order to reduce their influence, it is necessary to reduce the parasitic inductance in the circuit as much as possible. We take a boost converter as an example, and the conclusion can be extended to a buck converter. Figure 2 depicts the problem caused by the register inductance in the circuit: the MOSFET is open---the inductor current has been shorted by the MOSFET. The reverse capacitance of the diode is quickly charged, with a higher dv/dt at the node of the diode's positive terminal. When the MOSFET is turned on, the series inductance (LfT+LfD+LfC) increases the discharge time, thus increasing the switching loss of the MOSFET. At the same time, these inductors also generate noise.

The peak current is limited by the transistor. The transistor works like a current source. For a 2A MOSFET, the peak current may reach 10A. When this changing current passes through the inductor, it will generate a voltage proportional to the current change:

v=L×[di(t)/dt]

The entire transient change process is equivalent to a spike generator, so it is very necessary to reduce the seeking inductance by reducing the wire length, and using short and wide wires for the MOSFET, diode and Cout period. In addition, by controlling the gate drive The slope of the waveform can also be used to reduce noise. In order to limit the resistive voltage drop and the number of vias, the SMD components of the power stage must be arranged on the component side of the circuit board, and the leads of the power wires are also on the component layer. If possible, power is also routed on the same layer. To eliminate radiated areas, be careful to reduce the area of ​​power current loops.

When power lines must be routed on other levels, wires leading from the inductor or filter capacitor should be selected (for example, Cout of a buck converter or Cin of a buck converter). The current flowing through these wires is nearly continuous and produces no noise but only a resistive drop. If this line is distributed on the next layer of the component layer, the stray inductance generated will be smaller. To avoid common-mode impedance coupling, PGND, power ground, and common ground planes should be separated.

Capacitors and other components

High-capacity, low-ESR capacitors are expensive, and proper layout will maintain their performance and reduce output noise from 150mV to 50mV. Ripple is directly related to factors such as inductance, capacitor ESR, and switching frequency, but high-frequency noise (spikes) depends on parasitic components and switching behavior. Based on the switching frequency, we can infer that the peak frequency spectrum ranges from 1MHz to 10MHz.

For the inductive component, the changing current (di/dt) caused by the switching action flows through Lp1 causing the controller Vcc to overshoot, calculated as follows:

v(t)=L×[di(t)/dt]

When L=10nH, ΔI=1A, Δt=50ns, ΔV0.2V

Pay attention to cutting off the power leads and arranging PGND reasonably. In addition, care should be taken to avoid passing other connections through the power loop. The lead used to distribute the input voltage should be connected before the input capacitor and the Vcc connection of the controller. The output voltage lead should be after the connection point of the high frequency output capacitor.