More perspectives on interleaved ADCs

The benefits of interleaving can benefit multiple market segments. The most useful benefit is the increased bandwidth through the wider Nyquist zones of the interleaved ADCs. Again, let’s start with the example of two 500MSPS ADCs interleaved to create a 1000MSPS sampling rate. By interleaving the two ADCs, the bandwidth can be increased significantly. Note that fS is shown for one converter; the interleaved converter sampling rate is equal to 2 X fS.

Two Interleaved ADCs – Nyquist Zone

It can provide advantages for a variety of different applications. Intrinsic system requirements in many designs are ahead of commercial ADC technology. No matter how high the ADC sampling rate is, the market seems to demand higher rates. Interleaved structures can fill the technology gap. Military and aerospace applications are requiring higher bandwidths for better spatial recognition. In addition, there is a need for increased channel bandwidth in back-end communications.

Just as cellular standards have increased channel bandwidth and the number of operating frequency bands, the requirements for the available bandwidth of ADCs have also increased. In some markets and applications, there is also a need to move to direct RF sampling, which allows for fewer stages in the radio design and the removal of demodulators. A sufficiently high sampling rate of the ADC also has the potential to reduce clock requirements. Therefore, it is feasible to align the ADC with the DAC clock, simplifying the system design. In instrumentation and measurement applications, higher bandwidth is required to acquire and measure signals.

Higher sampling rates provide more bandwidth for these applications. It makes frequency planning easier and reduces the complexity and cost of the antialiasing filters typically used at the ADC input.

With so many advantages, you have to ask what the price is for all of them. As with most things, there is no such thing as a free lunch. Interleaved ADCs offer higher bandwidth and other useful advantages, but they also come with some challenges.

How many converters can we combine? Let’s take a quick look at the clock requirements for interleaved ADCs:

This equation is easy to solve for m = 2. However, when m is equal to another number (such as 8), the clock requirements become very complicated. Substituting m in and solving the equation for 8 converters, the required clock phases are: 0, 45, 90, 135, 180, 225, 270, and 315 degrees. This is not a problem if the input clock frequency is low, but the point of using an interleaved structure is to achieve a high sampling rate.

In reality, the clock frequency is 1GHz. This means that the clock circuit must be able to divide the input clock and create phases that are 125ps apart; at the same time, it must do this accurately. Any error or jitter in the clock will degrade performance.