Detailed explanation of several key layout techniques when designing high-frequency switching power supplies

Today's switching regulators and power supplies are more sophisticated and powerful, but one of the challenges they face is that the ever-increasing switching frequency makes PCB design more difficult. PCB layout is becoming a watershed that distinguishes a good switching power supply design from a bad one. This article will provide suggestions on how to achieve a good PCB layout the first time.

Take, for example, a 3A switching regulator that steps down 24V to 3.3V. At first glance, a 10W regulator wouldn't seem too difficult, so designers are often tempted to jump right into the construction phase.

However, using design software such as National Semiconductor's Webench, we can see what problems this idea actually encounters. After entering the above requirements, Webench will select the LM25576 from the company's 'Simpler Switcher' series (a 42V input device including a 3A FET). It uses a TSSOP-20 package with a thermal pad.

Webench options include design optimization for size or efficiency, which are all single options. That is, high efficiency requires low switching frequency (reducing switching losses in FETs). Therefore, large inductors and capacitors are required, which requires more PCB space.

Note: The maximum efficiency is 84%, and this maximum efficiency is achieved when the input-to-output voltage difference is low. In this case, the input/output ratio is greater than 7. In general, using two stages reduces the stage-to-stage ratio, but the efficiency obtained by using two regulators is not better.

Next, we select the highest switching frequency for the smallest PCB area. High switching frequencies are most likely to cause layout problems. Webench then generates a schematic with all active and passive components.

Circuit Design

Refer to the current paths in Figure 1: the path through which the FET flows when it is on is marked in red; the path through which the FET flows when it is off is marked in green. We observe two different situations: the two-color area and the area with only one color. We must pay special attention to the latter case because the current alternates between zero and full-scale voltage. These are all high di/dt areas.

Figure 1

AC with high di/dt generates a large magnetic field around the PCB conductors, which is a major source of interference to other components within the circuit and even other circuits on the same or adjacent PCB. Since the common current path is assumed to be non-AC, it is not a critical path and the impact of di/dt is much smaller. On the other hand, these areas are more loaded over time. In this case, the common path is from the cathode of the diode to the output and from the output ground to the anode of the diode. When the output capacitor is charged and discharged, the capacitor has a very high di/dt. All the lines connecting the output capacitor must meet two conditions: they must be wide due to the large current; and they must be as short as possible to minimize the impact of di/dt.

Figure 2

In fact, the designer should not use the so-called traditional layout method of running wires from Vout and ground to the capacitor. These wires should carry large AC currents. It is better to connect the output and ground directly to the capacitor terminals. Therefore, the alternating current only appears on the capacitor. The other wires connecting the capacitor now carry almost constant current, and any problems related to di/dt are solved.

Figure 3

Grounding is another area where misunderstanding often occurs. Simply placing a ground plane on 'level 2' and connecting all ground connections to it will not give good results.

Figure 4

让我们看看为什么。我们的设计范例显示，有高达3A的电流必须从接地流回到源端(一个24V汽车电池或一个24V电源)。在二极管、COUT、CIN和负载的接地连接处会有大电流。而交换式稳压器的接地连接流经的电流小。同样情况也适用于电阻分压器的接地参考。若上述全部接地接脚都连至一个地平面，我们会遇到接地弹跳(ground bouncing)。虽然很小，但电路中的感应点(如藉以获得反馈电压的电阻分压器)将不会有稳定的参考接地。这样，整个稳压精密度将受到极大影响。实际上，我们甚至会从隐藏在level 2的地平面中得到‘震铃(ringing)’，而该震铃非常难以定位。

Additionally, high-current connections must use vias to the ground plane, which is another source of interference and noise. A better solution is to use the CIN ground connection as a star node for all high-current ground wires on the input and output sides of the circuit. The star node connects the ground plane and the two low-current ground connections (IC and voltage divider).

Figure 5

Now the ground plane is clean: no high currents, no ground bounce. All high current grounds are connected in a star pattern to the CIN ground. All the designer has to do is to make the ground traces (all on the first layer of the PCB) as short and thick as possible. In this context, saving copper will basically not achieve good results.

Node impedance

High impedance nodes should be checked as they are easily disturbed.

The most critical node is the feedback pin of the IC, where the signal is taken from the resistor divider. The FB pin is the input of an amplifier (such as the LM25576) or a comparator (such as in the case of a hysteretic regulator). In both cases, the impedance of the FB point is quite high. Therefore, the resistor divider should be placed to the right of the FB pin, and a short wire should be connected from the middle of the resistor divider to FB. The wire from the output to the resistor divider is low impedance, and a longer wire can be used to connect to the resistor divider. The focus here is on the wiring method rather than the wire length.

Other nodes are not as critical. So don’t worry about the switch node, the diode, COUT, the VIN pin of the switch IC, or CIN.

Wiring Tips

The wiring technique makes a difference for the resistor divider. The wire goes from COUT to the resistor divider and its ground goes back to COUT. We must make sure that this loop does not form an open area. An open area will act as a receiving antenna. If we can ensure that the ground plane under the wire is not disturbed, then the area formed by the wire and the ground under it and between level 1 and level 2 should be undisturbed. Now, we can see why the ground should not be placed on level 4, because the distance is significantly increased.

Alternatively, the ground connection of the resistor divider can be routed to level 1, making the two wires parallel and as close as possible to minimize the area. These observations apply to all wires through which the signal flows: sensor connections, amplifier outputs, and inputs to ADCs or audio power amplifiers. For every analog signal, it must be processed so that it is not easy to introduce noise.

The requirement to minimize open areas whenever possible also applies to low impedance conductors; in this case, we have a potential source (antenna) of interfering signals to other parts of the PCB or other devices. Note: When it comes to open areas, smaller is better.

Two wires are also critical: from the IC's switch output to the diode and inductor node; and from the diode to the node. Both of these wires have high di/dt: either the switch is conducting or the diode is flowing current, so these wires should be as short and thick as possible. The wires from the node to the inductor and from the inductor to COUT are less critical. In this case, the inductor current is relatively constant and changes slowly. All we have to do is make sure it is a low impedance point to minimize voltage drop.

Actual layout

Let's look at a good layout (below). The main components are a controller in an MSOP-8 package used with external FETs.

Observe the space around CIN. Note: The ground point of this capacitor is directly connected to the diode anode. You cannot make the wire in 'power ground' too short! FET[SW] should be moved up a few mm to shorten the cathode-inductor-FET wire.

The COUT area is not visible. But we can see that the resistor divider (FB1-FB2) is very close to the IC. FB2 is connected to another ground plane, and the IC ground pin is treated the same way. The 'signal' ground is connected to the ground plane using three vias, and the 'power' ground is also connected to the GND pin of the PCB using three vias. In this way, the 'signal' ground will not 'see' any ground bounce of the 'power' ground.

If you follow a few simple rules (only some of which are discussed in this article), you will have no trouble with your PCB layout. Thinking carefully about the PCB layout before you start will go a long way in saving time and help you save time dealing with switching power supply anomalies.