Low voltage, ultra-low power sawtooth oscillator

This sawtooth oscillator circuit requires less than 3.2μA of current and operates at less than 1V, making it a useful building block for extremely low power and low voltage operation. It can be used as the basis for a PWM control loop, a timer or a voltage-controlled oscillator (VCO), or as a capacitor-to-frequency converter. The circuit is elegant in that it uses the open-drain comparator output to make a precise switched current source, and it uses the latch function to make a simple comparator into a window comparator without additional components.

The circuit is also attractive because of its small size, few external components, low supply current, and ability to maintain constant amplitude and frequency as the battery voltage varies. Unlike conventional op amp astable multivibrators, this design uses a precision reference voltage to set the comparator threshold rather than a combination of the op amp output swing and resistor feedback.

This fixed frequency design based on the ratio usually produces a variable amplitude sawtooth waveform, which is undesirable in a PWM control loop because it affects the loop gain. The benefit is that by changing R1 and R2, the ramp can be independently controlled to increase or decrease.

As shown in Figure 1, this circuit contains only eight components: two integrated circuits, four resistors, one capacitor, and one power bypass capacitor. The key parts are two analog building block ICs from Touchstone Semiconductor, which are packaged in 4mm2 TDFN packages (TS12011 and TS12012), each containing an op amp, a comparator, and a reference. With these features, the design can be made ultra-small and simple.

The advantage of this circuit is its small size and few external components.

The circuit operates as follows: An adding integrator feeding a window comparator generates a sawtooth waveform. The feedback action of the amplifier holds the integrator summing node at VREF, thereby balancing the fixed positive reference current set by R1 with the larger amplitude switching negative current set by R2. The lower comparator block produces an open-drain output; when its output is low, current is pulled from the summing node through R2: IR1 = (0.87 × VREF - 0.58 × VREF) / R1, IR2 (switch current) = 0.58 × VREF / R2. If IR2 is set to 2 × IR1, a symmetrical triangle wave will be generated.

The frequency settings are as follows:

Where V is the difference between 0.87×VREF and 0.58×VREF. Here, f=850Hz.

Figure 2 shows the sawtooth and pulse waveforms.

The window comparator uses the TS12012's built-in latch function to provide hysteresis. The latch function has the following characteristics: when pulled low, the comparator output remains valid and detects the input state until the input crosses. When the ramp crosses the lower threshold of 0.58×VREF, the comparator in IC2 is set; when the ramp crosses 0.87×VREF, the comparator in IC2 is reset. The reset pulse is momentary, but it causes the latch to enter a state where crossing the comparator input causes it to repeatedly set and reset (this occurs because the switching reference current causes the integrator to enter a negative slope). The end result is that no glue logic is required.

The supply voltage is as low as 0.9V, and the VDD current is only 3.2μA. The maximum operating frequency is limited to about 3kHz by the op amp slew rate and simple delays. The VCO function can be generated by disconnecting R1 and powering it with a voltage source greater than 0.58×VREF.