Low-power design of BIST based on LFSR optimization

Introduction

As portable devices and wireless communication systems are increasingly used in real life, the power consumption of design for testability (DFT) has attracted more and more attention from VLSI designers. Because the power consumption of the circuit in test mode is much higher than that in normal mode, it will inevitably bring a series of problems such as battery life, chip packaging, and reliability. With the development of integrated circuits, built-in self-test (BIST) has become the preferred design for testability to solve SoC test problems because of its many advantages (such as reducing the performance and cost requirements of automatic test equipment, being able to perform at-speed testing, and helping to protect the intellectual property rights of IP cores).

In BIST, linear feedback shift registers (LFSRs) are often used as test pattern generators (TPGs). LFSRs must generate very long test vector sets to meet the requirements of fault coverage, but these vectors consume a lot of power.

In addition, in the system working mode, the continuous functional input vectors applied to a given circuit have important correlations, while the correlations between the continuous test patterns generated by the LFSR are very low. Therefore, the flipping activity of nodes in the circuit will increase during self-test, resulting in increased power consumption.

2 Power consumption analysis and WSA model

The sources of power consumption in CMOS circuits are mainly divided into two types: static power consumption and dynamic power consumption. Leakage current or other currents that continuously flow out of the power supply cause static power consumption. Dynamic power consumption is caused by short-circuit current and the charging and discharging of load capacitance, which is caused by functional jumps during normal operation of the circuit. It includes functional jumps, short-circuit currents, competition and risk, etc. For CMOS technology, dynamic power consumption is currently the main source of circuit power consumption.

The power consumption of each switch on node i is:

Where Si is the number of flips in a single cycle, Fi is the fan-out of node i, C0 is the minimum output load capacitance, and VDD is the power supply voltage. As

can be seen from formula (1), the power consumption estimation at the gate level is related to the product of Si and Fi and the number of flips of node i. The fan-out of the node is determined by the circuit topology, and its number of flips is estimated by the logic simulator. This product is called the weighted switching activity (WSA) of node i. During the test process, WSA is the only variable of the power consumption Ei of node i, so WSA can be used as the power consumption estimate of the node. For a pair of continuous input vectors TPk=(Vk-1, Vk), the total WSA of the circuit is:

Where i is the number of all nodes in the circuit, and S(i, k) is the number of flips of node i stimulated by TPk.
According to formula (2), considering the test vector TS of length L as the input vector of the circuit, the total WSA of the circuit is:

According to the above expressions of power and energy consumption, given a circuit design of CMOS process and power supply, the following conclusions can be drawn:
(1) The number of transitions of node i in the circuit becomes the only parameter that affects energy, maximum power consumption and average power consumption.

(2) The frequency of the clock in the test also affects the average power consumption and maximum power consumption.
(3) The test length, that is, the number of test vectors applied to the circuit under test (CUT), only affects the total energy consumption.

3 LFSR Optimized Low Power Method

Through the power consumption analysis of the test process, it can be seen that when selecting a BIST low power solution, on the one hand, it can be achieved by reducing the length of the test sequence (but this method often sacrifices the fault coverage), and on the other hand, reducing the WSA value can also achieve system power consumption reduction.

In the BIST structure, the linear feedback shift register (LFSR) is easy to integrate in the DFT scanning environment due to its simple structure, regularity, very good random test vector generation characteristics, and very small confusion probability when used to compress test responses. Therefore, when upgrading from scanning DFT design to BIST design, LFSR becomes the most widely used vector generation structure in BIST due to its low hardware overhead.

BIST structures based on LFSR optimization can be divided into two types: test-per-scan and test-per-clock. The area overhead caused by test-per-scan technology is small, the test structure is simple, and it is easy to expand. Test-per-clock can realize vector generation and response compression in one cycle, and can complete fast testing.

3.1 Scan-based test-per-scan method
3.1.1 Basic structure
The goal of test-per-scan built-in self-test is to reduce hardware overhead as much as possible. This structure uses a combination of LFSR and register to replace LFSR at each input and output port. Figure 1 is the basic circuit structure of test-per-scan built-in self-test. Under the built-in self-test vector, LFSR generates test vectors and shifts the test vectors to the input of the circuit under test (CUT) through the scan shift register. At the same time, the response is shifted into the LFSR and compressed.

3.1.2 Principle

Full scan or partial scan design will generate relatively large power consumption due to shifting. The scan-based test-per-scan low-power design method requires modifying the standard scan design to reduce the state transition activity rate. The design modification includes some gating logic used to shield the scan path activity during the shift, and the synthesis of additional logic used to suppress random patterns.

3.1.3 Partial scan algorithm

According to the above scan design principle, after eliminating the redundant patterns in the test sequence, the partial scan algorithm shown in Figure 2 is used to perform partial scan design on the circuit to be tested. The steps are as follows:

① First, delete all vertices corresponding to the self-feedback sequential logic.
② Find all strongly connected components (SCC) in the data flow graph.

③ Delete the largest vertex among all the vertices of SCC in turn.

The reference uses the above algorithm to scan the BIST test of ISCA89 benchmark circuit, and uses ATPG tool and simulation tool VCS fault simulation and functional simulation. Table 1 lists the test coverage, average power consumption and peak power consumption data.

From the data in Table 1, it can be seen that partial scan has very little impact on the test coverage of the circuit under test (<3.5%). After the circuit is designed with partial scan, the number of scan registers is greatly reduced, so the number of registers that need to be triggered simultaneously in the scan shift cycle is also greatly reduced, which causes the number of internal node flips of the circuit under test to be greatly reduced, and the purpose of reducing the average power consumption and peak power consumption of BIST can be achieved.

3.2 Test-per-clock method based on clock

3.2.1 Basic structure

The basic structure of a test-per-clock built-in self-test is shown in Figure 3. Each test clock L2SR generates a test vector. The multiple-input signature register (MISR) compresses a response vector.

3.2.2 Principle

In scan testing, the main power consumption includes logic power consumption, scan power consumption and clock power consumption. The methods given above mainly focus on reducing logic power consumption or scan power consumption, but do not reduce clock power consumption. The clock-based low-power test-per-clock method can reduce these three power consumptions at the same time. This method uses a low-power test-per-clock BIST structure. After modifying the LFSR, it is used as a TPG to generate low-power test vectors. Using this modified clock scheme will reduce the jump density of the circuit under test, TPG and the clock tree feeding the TPG. The power consumption during BIST is reduced by reducing the state transition activity rate of the circuit under test, TPG and clock tree.
Since the test patterns derived from the standard scan structure can be directly used in the low-power scan structure, this method is basically consistent with the fault coverage and IC test time achieved by using the traditional scan structure. Compared with the traditional scan structure, the area overhead is very small and there is no loss in circuit performance.

3.2.3 Low-power test vector generation

For the test-per-clock structure, reducing test power consumption is mainly achieved by optimizing the test vector, and the test vector generation technology refers to the technology of generating deterministic test vectors.

When generating test patterns, the test vector generation method not only needs to achieve the traditional ATPG purpose, but also needs to consider reducing power consumption during testing. There are two types of ATPG-based methods: ① Integrated ATPG optimization method, in which the test pattern is optimized for low power consumption during test generation; ② Post-ATPG optimization method, in which the test pattern is first generated by traditional ATPG and then optimized for power consumption.

(1) The steps of test vector generation combined with simulated annealing algorithm are: first, the test pattern is grouped into two parts, namely, a number of valid test vector groups and invalid test vector groups according to the simulated annealing algorithm; then, according to the algorithm principle, the control code for controlling the operation of LFSR is generated; under the action of these control codes, LFSR skips a large number of invalid test vectors and generates a streamlined test vector sequence consisting of valid test vectors. Its basic process is shown in Figure 4.

(2) Combining with evolutionary algorithms Based on the principle of test vector generation technology, a test pattern generator based on genetic algorithms is used to calculate redundant test patterns. In redundant test patterns, a fault is covered by several different sequences. Then an optimization algorithm is used to select an optimal subset from the previously calculated test sequence combinations to minimize its peak power without affecting the fault coverage. The reference uses the combinational circuit in the ISCAS'85 Bench-mark as the experimental circuit. While keeping the fault coverage unchanged, the test power consumption a of the circuit to be tested is compared with the test power consumption b of the BIST structure using the simulated annealing algorithm. The results are shown in Table 2.

As shown in Table 2, when the same fault coverage is met, WSA is greatly reduced after the simulated annealing algorithm is used to group the test vectors, and the total WSA improvement rate is between 73.44% and 94.96%. Due to the reduction of test vectors, the test time is also greatly shortened.

4 Conclusion

The BIST structure that uses linear feedback shift registers to generate test vectors can be divided into two categories: test-per-scan and test-per-clock. The corresponding low-power BIST test methods are also targeted at test-per-scan and test-per-clock structures. For the test-per-scan structure mode, reducing test power consumption is mainly achieved by optimizing the scan chain; for the test-per-clock structure mode, reducing test power consumption is mainly achieved by optimizing the test vector. The area overhead caused by the test-per-scan technology is small, the test structure is simple, and it is easy to expand; while the test-per-clock can achieve vector generation and response compression within one cycle, and can complete fast testing. Of course, with the in-depth study of test power consumption, there will be better methods to optimize power consumption, fault coverage, system performance and other issues.