13.2A 50mW Bandpass SD ADC (Analog-to-Digital Converter)

　　The main challenge for portable wireless receivers is to maximize their dynamic range while minimizing power consumption. A direct conversion receiver with a pair of time-continuous, low-pass analog-to-digital converters (ADCs) consumes very little power, but is susceptible to problems such as poor orthogonality, DC offset, and low-frequency distortion, which limit the dynamic range of the product. On the other hand, a double-conversion superheterodyne receiver does not have these limitations, but typically consumes more power due to its increased complexity and the need to digitize the higher intermediate frequency (IF) signal. This article describes a mixer and time-continuous bandpass SD ADC assembly with a frequency range of 10 to 300 MHz, a bandwidth of 333 kHz, and a dynamic range of 90 dB. The circuit consumes 50 mW, demonstrating that a low-power, high-performance double-conversion superheterodyne receiver is achievable.

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　　Figure 1 compares two methods of digitizing an IF signal. The first method requires several high-power blocks, namely, variable gain amplifier (VGA), anti-aliasing filter (AAF), and ADC, while the second method replaces these blocks with a bandpass SD ADC with an LC resonant circuit. The bandpass SD ADC is protected against inherent aliasing with the help of a time-continuous loop filter and eliminates the need for the AAF. The ADC has a higher dynamic range because of its lower input noise and its current-mode input provides a stronger signal.

The second simple topology offers a power saving advantage by incorporating these two power hungry blocks into the ADC.

　　Figure 2 shows the ADC architecture in more detail. Given the above discussion, the transconductance of the low noise amplifier (LNA) plus mixer is considered to be gm = 10mA/V. The output current of the low noise amplifier plus mixer, 2mApp, is directly used as the input of the ADC without unnecessary IV or VI conversion. The current of the 8-element current-mode DAC (IDAC) minus the feedback digital output current generates an error current that drives the LC resonant circuit. The LC resonant circuit consists of two external 5.6mH inductors and a capacitor. The capacitor value is fine-tuned to within 1% of the required value through a 9-bit on-chip capacitor array. The effective impedance of the LC resonant circuit in the relevant frequency band is Z = 6KW, which will cause a voltage swing of 12VPP. If it were not for the feedback from the IDAC, the feedback from the IDAC would only result in the following voltage swing. The maximum effective gain of the front-end circuit is gmZ = 60, which will reduce the noise of the ADC back-end from 0.001 to only 0.001 when the low noise amplifier has an input signal. Since this noise is 8dB lower than the input noise of the low noise amplifier/mixer, the back end of the ADC has little effect on the IC noise characteristics. Since the LC resonant circuit does not generate noise, is distortion-free and consumes no power, it is an ideal first resonator in a bandpass SD ADC.

　　VGAs are often used to reduce the input noise of an ADC by gain when the signal is weak. However, the VGA in Figure 2 is an internal component of the ADC and its main purpose is to reduce power consumption when the signal is weak. To balance the current of large signals, the total current of the IDAC components must be 2mA, but when the signal is weak, the current of the components can be reduced (reduced by 1/4 in this solution) to save power. Comprehensively changing IADC can change the ADC accordingly, so that the AGC function can be realized. Comprehensively reducing the IDAC can reduce the signal swing at the back end of the ADC and use the variable gain components in the figure to make the circuit most effectively compensated. In order to maintain the dynamic range of the modulator, the gain of the VGA will change inversely with the comprehensive fluctuation of the IDAC. The VGA is a module with a variable gm value and is controlled by changing the tail current in the differential pair of non-degenerate bipolar junction transistors (BJTs).

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　　The ADC's second resonator also uses an LC resonant circuit. The VGA and active RC resonator in Figure 3 consume 2mA of current and meet the second-stage dynamic range requirement without external components. A programmable capacitor array enables tuning of the RC resonator.