Increasing the number of outputs from a clock source using low-jitter LVPECL fanout buffers

Device Connections/References
 

ADF4351: Fractional-N PLL Synthesizer with Integrated VCO

ADCLK948: Clock Fanout Buffer with Eight LVPECL Outputs

Evaluation and Design Support

Circuit Evaluation Board

ADF4351 evaluation board (EVAL-ADF4351EB1Z)

ADCLK948 Evaluation Board (ADCLK948/PCBZ)

Design and Integration Documentation

Schematics, layout files, bill of materials

Circuit Function and Advantages

Many systems require multiple low jitter system clocks for mixed signal processing and timing. The circuit shown in Figure 1 interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage controlled oscillator (VCO) to the ADCLK948, which provides up to eight differential, low voltage positive emitter coupled logic (LVPECL) outputs from one differential output of the ADF4351.

Modern digital systems often require the use of many high quality clocks with different logic levels than the clock source. To ensure accurate power distribution to other circuit elements without loss of integrity, additional buffering may be required. The interface between the ADF4351 clock source and the ADCLK948 clock fanout buffer is described here, and the measured results show that the additive jitter associated with the clock fanout buffer is 75 fs rms.

Circuit Description

The ADF4351 is a wideband PLL and VCO consisting of three independent multiband VCOs. Each VCO covers a range of approximately 700 MHz (with some overlap between the VCO frequencies). This provides a basic VCO frequency range of 2.2 GHz to 4.4 GHz. Frequencies below 2.2 GHz can be generated using the internal dividers of the ADF4351.

To complete the clock generation, the ADF4351 PLL and VCO must be enabled and the desired output frequency must be set. The output frequency of the ADF4351 is provided through an open-collector output at the RFOUT pin, which requires a shunt inductor (or resistor) and a dc blocking capacitor.

The ADCLK948 is a SiGe low jitter clock fanout buffer that is ideal for use with the ADF4351 because its maximum input frequency (4.5 GHz) is just above that of the ADF4351 (4.4 GHz). The broadband rms additive jitter is 75 fs.

To emulate LVPECL logic levels, a DC common-mode bias level of 1.65 V needs to be added to the CLK input of the ADCLK948. This can be accomplished by using a resistor bias network. The lack of a DC bias circuit will result in degraded signal integrity at the output of the ADCLK948.

Common changes

Other frequency synthesizers with integrated VCOs, such as the ADF4350 fractional-N (137 MHz to 4400 MHz) and ADF4360 integer-N families, can also be used.

Other available clock fan-out buffers in the same family as the ADCLK948 are the ADCLK946 (6 LVPECL outputs), ADCLK950 (10 LVPECL outputs), and ADCLK954 (12 LVPECL outputs).

Circuit Evaluation and Testing

The EVAL-ADF4351EB1Z board was used as the clock source with minor modifications when evaluating this circuit. The EVAL-ADF4351EB1Z board uses the standard ADF4351 programming software, which is included on the CD that comes with the evaluation board. ADCLK948/PCBZ is also required and can be used without modification.

Equipment Requirements

The following equipment is needed:

. EVAL-ADF4351EB1Z evaluation board kit, including programming software

. ADCLK948PCBZ evaluation board

. 3.3 V power supply

. Two cables for connecting the 3.3 V power supply and the ADCLK948PCBZ

. Two equal lengths of shorter SMA coaxial cables

. High-speed oscilloscope (2 GHz bandwidth) or equivalent

. R&S FSUP26 spectrum analyzer or equivalent

. PC with Windows XP, Windows Vista (32-bit) or Windows 7 (32-bit)

An SMA coaxial cable is required to connect the RFOUTA+ and RFOUTA– pins of the EVAL-ADF4351EB1Z to the CLK0 and CLK1 pins of the ADCLK948PCBZ.

Functional Block Diagram

The ADCLK948PCBZ and EVAL-ADF4351EB1Z are used in this experiment. These boards are connected to the ADCLK948PCBZ via an SMA cable as shown in Figure 1.

Get Started

The UG-435 user guide details the installation and use of the EVAL-ADF4351EB1Z evaluation software. UG-435 also contains board setup instructions as well as the board schematic, layout, and bill of materials. The necessary modifications to the board are the insertion of 100 Ω resistors after the dc blocking capacitors. These resistors are connected to the 3.3 V supply and to ground. This should be done for both the RFOUTA+ and RFOUTA- pins to provide a common-mode voltage of 1.65 V (higher than the minimum required of 1.5 V). This may require the removal of solder mask near these transmission lines.

The UG-068 User Guide contains similar information on the operation of the ADCLK948/PCBZ evaluation board.


Logic Level Measurements

In this example, a Rohde & Schwarz RTO1024 oscilloscope is used with two RT-ZS30 active probes to accurately measure high-speed logic levels.

Install the ADF435x software on the PC. The specific steps are as follows:

1. Connect the EVAL-ADF4351EB1Z to the PC according to the hardware driver instructions in UG-435.

2. Program the ADF4351 PLL according to the ADF435x software screenshot (see Figure 3). In this example, an RF frequency of 1 GHz is selected.

3. Use two short SMA cables of equal length to connect the RFOUTA+ and RFOUTA− SMA connectors of the EVAL-ADF4351EB1Z board to the CLK0/CLK0 SMA connector of the ADCLK948/PCBZ board.

4. Connect the differential output OUT2/OUT2 of ADCLK948/PCBZ to a high-speed oscilloscope. See Figure 4 for a typical waveform of a 1 GHz output.

Phase Noise and Jitter Measurements

1. Repeat steps 1 to 4 of the “Logic Level Measurement” section.

2. Connect the unused CLK2 output of ADCLK948/PCBZ to a 50 Ω load (see Figure 5).

3. Connect the CLK2 output to the signal source analyzer via an SMA cable (see Figure 5).

4. Measure the jitter performance of the signal.

Figure 6 shows the phase noise at the output of the ADF4351, with an rms jitter of 325.7 fs. Figure 7 shows the phase noise at the output of the ADCLK948. The rms jitter is 330.4 fs.

The additive jitter of the ADCLK948 is calculated as follows: √(330.4(sup)2(/sup) - 325.7(sup)2(sup)) = 55.5 fs rms. The ADCLK948 data sheet specifies 75 fs rms.