A simple sawtooth generator operating at high frequency

Pulse width modulated signal generator circuits usually use an analog sawtooth oscillator function, but it can also be used for other applications. Figure 1 shows an inexpensive sawtooth generator that is used in low power applications with frequencies up to 10MHz or even higher, and where ramp linearity and frequency accuracy are not critical.

The circuit uses a Schmitt trigger as an inverter, connected to form an improved astable multivibrator. The output waveform is the voltage on the timing capacitor CT, which ramps up between the upper and lower threshold voltages of the inverter. The result of charging the RTCT network with a constant voltage is a ramp, so its response is exponential, and it is close to linear only in the early stage of the exponential rise.

Figure 1. A sawtooth waveform can be generated using a ramped charge and rapid discharge of CT. The upper and lower trip voltages of the Schmitt trigger limit the sawtooth waveform. See the text for VCC, CT, and RT values.

A simple trick to improve linearity is to charge the RTCT network with a larger voltage source. Capacitor C1 should have a value at least 10 times greater than CT and act as a charge pump. On the falling edge of the sawtooth waveform, when the gate output is low, capacitor C1 is quickly charged through diode D1 to VCC minus the forward voltage of D1. At the same time, CT is quickly discharged through D2.

When the drop in CT voltage reaches the lower trigger point of the Schmitt trigger, the gate output VT- returns to high. The charge on C1 makes the negative voltage of D1 equal to the sum of the capacitor C1 voltage and the gate high output voltage. D1 becomes reverse biased, and with the high output voltage of the gate, the RTCT network begins to charge to the voltage on C1. When CT reaches the upper trigger point of the Schmitt trigger, the gate output VT+ returns to low, and the cycle repeats.

The slope linearity is proportional to the sum of the VCC and VDD supply voltages. Since VDD is fixed at 5V, if VCC can be determined to a value higher than the inverter, the linearity of the slope can be improved. The nonlinear error of the slope can be estimated using the following formula:

MI is the initial slope of the ramp, and MF is the final slope of the ramp, and

By simulating the circuit with CT=100pF and RT=2.2kΩ and accepting the theoretical calculated values ​​in the above formula, we can get that when VCC and VDD are both 5V, the nonlinear error of the slope is 28%; when VCC is 10V and VDD is 5V, the error is 18%; when VCC is 15V and VDD is 5V, the error is 14%.

The breadboard circuit has VDD=VCC=5V, CT=100pF, and RT=2.2kΩ. IC1 is a standard dual-row 8-pin 74HC14 with a maximum propagation delay of 15ns, while the delay of the SN74LVC1G14 inverter with VDD of 5V is 4.4ns. The frequency is about 12.7MHz.

CT should be a low leakage film capacitor and should be selected to be small to reduce high energy charging and discharging. The value of CT should be selected to be large enough to be above the gate input capacitance and excess stray capacitance so that it does not introduce significant errors. RT should be selected to be small enough so that the load impedance, gate input, and stray capacitance do not introduce significant errors. Any CMOS Schmitt trigger inverter can be used to test the circuit. However, for improved frequency accuracy, a high-speed logic family with low propagation delay and high output current should be used, such as the single-gate SN74LVC1G14 from Texas Instruments.

When using the above formulas, the trigger threshold voltages, especially VT-, should be measured directly from the circuit under test. The rapid discharge of CT to ground through a finite propagation delay inverter will reset the lower limit of the ramp to below the lower threshold VT-. If the measured value of VT- is used, which takes this effect into account, the resulting error can be compensated.