High-speed control solution LED display solution

Figure 1 is the circuit principle of the high-speed control scheme LED display. The MCS51 series single-chip microcomputer is used to control the LED display; the random access memory 62512 is used as the data storage of the LED display to store the font data of the content to be displayed; the 8-row scanning method is adopted, and multiple LED dot matrix pieces share a group of row drive circuits; each LED dot matrix piece has a group of column drive circuits, and 74LS377 is used as the column drive latch. The CPU writes the font data to the latch of the column drive circuit through the parallel bus; the address decoding circuit is used to generate the chip select address of the LED dot matrix row drive circuit and column drive circuit.

Figure 1 High-speed control scheme LED display electrical principle

This solution has two characteristics: first, although the CPU still writes the font data to the latch of the column drive circuit through the parallel bus, the latch signal of the latch uses the CPU control signal RD instead of the conventional WR; second, the address decoding circuit ensures that the chip select address of the LED dot matrix column drive circuit and the logical address of a certain section of the data memory are overlapping, instead of the conventional usage, the two sets of addresses must be separated.

Due to some simple changes in the above circuit, the display control efficiency of the single chip microcomputer on the LED display will change significantly. The specific working process is as follows: Assuming that the address of the data memory has been loaded into the data pointer DPTR, execute the instruction "MOVXA, @DPTR". The function of this instruction is that the CPU reads the font data from the external data memory according to the direction of DPTR and reads it into the accumulator A; but in this circuit, since the chip select address of the LED dot matrix column drive circuit and the logical address of a certain section of the data memory overlap, that is, when executing the instruction "MOVXA, @DPTR", DPTR not only points to a certain address of the external data memory, but also selects a latch of a certain LED dot matrix column drive circuit. If the latch pin of the selected latch happens to have an input pulse at this time, the latch will also lock the font data sent from the external data memory. This input pulse is used as RD. RD is the read control signal sent by the CPU to the external data memory when executing the instruction "MOVXA, @DPTR". Since the timing of the read control signal RD and the write control signal WR of the MCS51 series microcontrollers are exactly the same [2], it is not surprising that RD replaces WR to implement the latch function. When this instruction is executed, it completes the reading of the data memory and the writing of the LED dot matrix at the same time, thus speeding up the display control process.

As mentioned before, when the parallel bus is used, it takes about 10 μs for the CPU to complete the process of writing the font data to the latch of the column drive circuit of the LED dot matrix. Now it only takes 4 μs, which is much faster, because now it only takes two steps to complete the process of writing the font data to the latch of the column drive circuit of the LED dot matrix. First, assign a valid address to the data pointer DPTR, then the CPU reads the font data from the external data memory according to the direction of DPTR, and at the same time, it also transmits the font data to the latch of the column drive circuit of the LED dot matrix. 2 instructions, 4 machine cycles, 4 μs. Here I want to add that when compiling the program of writing the font data to the latch of the column drive circuit of all LED dot matrix pieces, do not use loop instructions, because then each process will increase 2 μs; the method of programming the LED dot matrix piece by piece should be adopted. Although the program compiled in this way takes up space, it saves time. The design method of using space for time is sometimes a method worth trying for designers.

The latch control of the row drive latch of this circuit still uses the write control signal WR of the CPU without any change. The chip select signal of the row drive latch also comes from the address decoding circuit. In order to avoid mutual interference between the data memory and the LED dot matrix, the storage space of the data memory corresponding to this group of addresses is not used.

The design of the address decoding circuit should ensure that the chip select address of the LED dot matrix column drive circuit and the logical address of a certain section of the data memory overlap. The specific design example is as follows:

Assume that a certain LED display screen uses 240 LED dot matrix pieces, which can display 60 16×16 Chinese characters, and uses a MCS51 series single-chip microcomputer for high-speed control. The chip select addresses of the column drive circuit of these 240 LED dot matrix pieces should be 240, and the address decoding circuit must ensure that the effective address after decoding is greater than this number. The address decoding circuit in Figure 1 inputs the address signal A0~A7 and A11~A15, and does not connect to A8, A9, and A10. Using the 74LS138 decoder, 256 effective address lines can be obtained after three-level decoding. The first effective address line corresponds to the 8 addresses of the external data memory: 0000H, 0100H, 0200H, 0300H, 0400H, 0500H, 0600H, 0700H. The second valid address line corresponds to the 8 addresses of the external data memory: 0001H, 0101H, 0201H, 0301H, 0401H, 0501H, 0601H, 0701H. ... The 256th valid address line corresponds to the 8 addresses of the external data memory: 00FFH, 01FFH, 02FFH, 03FFH, 04FFH, 05FFH, 06FFH, 07FFH. Of these 256 valid address lines, 240 are chip select addresses for the column drive circuit, and the remaining are chip select addresses for the row drive circuit; if they are not enough, the row drive circuit can be controlled by serial bus. The above analysis results show that the I/O interface address of a LED dot matrix piece and the 8-byte address of the data memory have established an overlapping relationship. This is because each LED dot matrix piece has 8 rows, and each row corresponds to 1 byte of font data.

The above analysis results also show that the I/O interface addresses of all LED dot matrix slices and the address segment 0000H to 07FFH of the data memory have established a mapping relationship. The data memory 0000H to 07FFH stores exactly all the font data of a frame of image.