Design and implementation of battery online monitoring system

Batteries are an essential backup power source in the power system and there are many of them. Their service life and safety and reliability are of great concern to users. However, due to improper use or failure to maintain in time, individual batteries in the battery pack are often over-discharged or fail prematurely. When the backup power supply is put into use, individual batteries that are over-discharged or fail prematurely will seriously affect the discharge capacity of the entire battery pack and even cause the collapse of the entire power supply system. Therefore, in order to ensure that the electrical equipment can operate safely and reliably when the city power is cut off, and to avoid accidents and economic losses caused by over-discharge or failure of individual batteries during long-term use, real-time online monitoring of batteries and timely fault diagnosis have become an extremely important aspect of battery maintenance. The battery online monitoring system based on STC89C58RD+ microcontroller introduced in this paper can realize the status monitoring of the battery in the idle state or in the dynamic process of charging and discharging; timely alarm for abnormal conditions such as open circuit, short circuit, overvoltage, undervoltage and over-discharge inside the battery and store data for query; it can measure the voltage of multiple multi-cell batteries of 2V, 6V and 12V online; and improve the accuracy, automation and intelligence of battery monitoring. This paper specifically introduces the hardware design and software implementation of the system.

System hardware design

System hardware structure

The battery online monitoring system is based on the STC89 series STC89C58RD+ microcontroller and XILINX's XC9572-84. The peripheral circuit is mainly composed of voltage acquisition circuit, A/D conversion circuit, display driver circuit and keyboard circuit, as shown in Figure 1. The A/D conversion chip uses the 10-bit ADC TLC1549. The display driver chip uses MC14489B, which can drive a 5-bit common cathode digital tube. The lower 5 bits of the microcontroller's P1 port are used as the keyboard input port, and the extended RS485 interface is used for multi-machine communication. The following is a detailed introduction to the design and implementation of the STC89C58RD+, XC9572-84 devices and voltage acquisition circuit, A/D conversion circuit in the system.

Figure 1 System hardware structure diagram

Introduction to Microcontroller STC89C58RD+

STC89C58RD+ is a microcontroller of STC89 series. It is not only fully compatible with 80C51, but also has new features: 32Kb Flash program memory, 32Kb DataFlash data memory, 1208B RAM data memory, and internal watchdog (WDT); the switch state of ALE signal can be set, thus reducing EMI; it has 8-level programmable interrupt sources with 4 priorities, system programmable (ISP) and application programmable (IAP) features, rich on-chip resources, high integration, and easy to use. STC89C58RD+ schedules the work of the system, realizes the setting of external input parameters, the test and display of battery voltage, and the indication of battery working status.

Logic programming device XC9572-84 (CPLD)

Since there are many battery cells to be monitored, many I/O ports are required. With traditional design methods, multiple chips such as 74HC273, 74HC00, 74HC138, CD4514, etc. are needed to realize the monitoring. The large number of device types and quantities increases the size of the PCB and also increases the instability of the system. This system uses the CPLD device XC9572-84 of the XILINX series, which has a total of 72 macro units, 69 I/O ports, 1600 gates, and 72 registers, which can integrate the above-mentioned multiple chips. The device has in-system programmability and contains advanced data confidentiality features. It can completely protect the programming data from being illegally read and erased. Each I/O port has a programmable output slew rate control bit to reduce system noise. It uses fast flash memory technology with low power consumption. Each I/O port has a strong driving capability and the load current can reach 24mA. XC9572-84 receives data and addresses from the microcontroller, controls the selection of each solid-state relay (G3VM-402C) and the A/D conversion, and achieves the function of collecting voltage. The use of CPLD devices reduces the number and types of devices required by the system, simplifies PCB layout and wiring, reduces system size and saves costs, facilitates system debugging, and is conducive to mass production.

Figure 2 Voltage acquisition circuit

Voltage acquisition circuit

The voltage acquisition circuit directly affects the accuracy of the voltage test, so whether the acquisition circuit is designed appropriately is crucial to the entire system. There are two ways to measure the voltage of each battery: ① directly collect the voltage of each battery. ② collect the total voltage of (n+1) batteries, subtract the total voltage of n batteries to get the voltage of the n+1 battery. The first voltage acquisition is accurate and safe. Although the second circuit is simpler, when there are many battery cells, the collected voltage is too high, which is unsafe and will cause large errors. Therefore, the first method is selected. The voltage acquisition circuit is required to be safe and the collected voltage must be sufficiently stable. The battery pack of this system is connected in series, BAT1+ is connected to the positive electrode of the first battery, BAT2+ is connected to the positive electrode of the second battery (the negative electrode of the first battery), and so on. Up to 41 batteries can be connected in sequence. After the XC9572-84 analog switch selects G3VM-402C, the voltage of 1 to n batteries is released to the voltage bus BUS1+ and BUS1- in sequence. The circuit uses the operational amplifier LM358 as the signal amplifier. Its front stage is a differential amplifier and the back stage is a voltage follower, so that TLC1549 can obtain a stable sampling voltage, as shown in Figure 2. 1VD0 and 1VD1 use FR104 high-speed switch tubes to protect the internal circuit of the operational amplifier. The differential gain is A=0.2, and the specific derivation is as follows:

(Ua-Up)/1R12=Up/1R14; ①

(Ub-Un)/1R11=(Un-Vo)/1R13; ②

Note the "virtual short" characteristic of the op amp, with Up=Un; combining equations ① and ②, we get Vo=((1R11+1R13)/1R11)·(1R14/(1R12+1R14))·Ua-1R13/1R11·Ub; select resistors to satisfy the relationship 1R13/1R11=1R14/1R12, the output voltage can be simplified to Vo=1R13/1R11·(Ua-Ub), so the voltage amplification factor A=Vo/(Ua-Ub)=1R13/1R11=0.2.

A/D conversion circuit

The A/D conversion of this system uses an off-chip serial bus 10-bit high-speed and high-precision dedicated integrated circuit TLC1549, which has low power consumption, small size, occupies less resources of the single-chip computer, and has the characteristics of convenient connection and simple programming. The output voltage of the voltage acquisition circuit is connected to the A/D conversion channel of TLC1549. Under the action of the clock pulse signal, TLC1549 converts the voltage into a 10-bit binary digital signal, and outputs the result of the last A/D conversion in the form of 10-bit binary numbers in sequence, and then transmits it to the single-chip computer for processing through optoelectronic isolation, as shown in Figure 3.

Figure 3 A/D conversion circuit

Points to note during hardware design

1 The system uses multiple power supplies. The power consumption of the system should be considered to select an appropriate power supply, and the power supply voltage should be relatively stable.

2 The voltage acquisition part uses a solid-state relay (G3VM-402C). Since there are many battery cells and the voltage is relatively high, attention should be paid to the protection of the internal circuit, and resistors with appropriate power can be used. The resistance accuracy of the amplifier circuit is relatively high, and metal film resistors with an accuracy of 1% can be selected; the circuit design should avoid the direct-through phenomenon caused by the simultaneous opening of multiple solid-state relays, which will cause multiple batteries to short-circuit and damage the voltage acquisition circuit.

3 The reference power supply of the A/D conversion chip must be very stable. The reference power supply and the chip working power supply should use different common ground power supplies to ensure the stability of the reference power supply of the A/D conversion chip. In order to reduce interference, the clock and chip select signals are optically isolated from the microcontroller and CPLD.

4 The layout of the device and the wiring of the PCB diagram adopt modularization, separation of AC and DC, separation of strong current and weak current, separation of digital ground and analog ground, and attention to the layout of power lines and ground lines.

System software design

In the software programming of the single-chip microcomputer, the Windows integrated development environment μvision2 of Keil C compiler is used as the software development platform, and the C51 high-level language is used for programming. This language is a special high-performance programming language for the 80C51 series of single-chip microcomputers. It is programmed in C language that conforms to the ANSI standard, which is easy to improve, expand and transplant. It can operate the hardware and can generate extremely high-speed and extremely concise target code. It is completely comparable to assembly language in terms of code efficiency and execution speed, and there are very rich library functions that can be directly called by users, which greatly improves the efficiency of program writing and can provide users with high-quality program codes. The hardware description language Verilog HDL is used to program the CPLD.

Points to note when programming MCU software

1 The keyboard is read in the timer interrupt service program, and the keyboard is debounced using the interrupt interval time. There is no need to write another delay program, which improves the CPU utilization efficiency. The keyboard value is stored in the data buffer, and the content of the data buffer is read in the main program to execute the keyboard function subprogram.

2 The battery voltage acquisition is executed in the interrupt program. Since the opening and closing time of the solid-state relay is 1ms, there must be a certain delay when the channel is selected so that the battery acquisition voltage can be established and stabilized before starting the A/D conversion.

3 According to the working principle of the A/D conversion chip TLC1549, the currently output data is the result of the previous A/D conversion. Therefore, the first A/D conversion result of a battery voltage sampling should be discarded, and the remaining conversion results should be retained and processed.

Figure 4 MCU software programming flow chart

4 According to the characteristics of DataFlash of STC89C58RD+, ISP/IAP command must be started when data is written. CPU waits for IAP action timing before continuing to execute the program. Interrupt (EA) must be turned off first. To write data into DataFlash memory, sectors cannot be crossed. If a sector is to be erased and some bytes of the content need to be protected, it must be read into the RAM inside the microcontroller and saved, then the sector is erased, and then the saved data is written back to the sector.

Verilog HDL Programming of CPLD

The advantages of programming hardware with the hardware description language Verilog HDL are that it is easy to understand, easy to maintain, fast in debugging circuits, and there are many easy-to-master simulation, synthesis, and layout and routing tools. You can also use C language with Verilog HDL to perform pre- and post-routing simulations of logic designs to verify whether the functions are correct. Due to space limitations, the following is a Verilog HDL program for some modules

module REG8 ( CLRB, D, CLK, Q ); //8-bit data latch

input CLRB, CLK;

input [7:0] D;

output [7:0] Q;

reg [7:0] Q;

always @(posedge CLK or negedge CLRB)

Q <= ( !CLRB )? 0: D;

endmodule

module DECODE4_16( E1,A,Y ); //4-16 decoding

input E1;

input [3:0] A;

output [15:0] Y;

reg [15:0] Y;

always @( E1 or A )

if(E1==0 )

begin

case(A)

0:Y=16'b1111111111111110;

1:Y=16'b1111111111111101;

2:Y=16'b11111111111111011;

3:Y=16'b11111111111110111;

4:Y=16'b11111111111101111;

5:Y=16'b1111111111011111;

6:Y=16'b1111111110111111;

7:Y=16'b1111111101111111;

8:Y=16'b1111111011111111;

9:Y=16'b1111110111111111;

10:Y=16'b1111101111111111;

11:Y=16'b1111011111111111;

12:Y=16'b1110111111111111;

13:Y=16'b1101111111111111;

14:Y=16'b10111111111111111;

15:Y=16'b0111111111111111;

endcase

end

else

Y=16'b1111111111111111;endmodule