Power management poses challenges

As cellular phones become more advanced, the power consumption of the system during operation and the power consumption during standby are also increasing. Therefore, the power management design of portable wireless devices faces new challenges in I/O interface, energy management and battery life.

Digital designers have led the industry in implementing microprocessors using ultra-deep submicron (0.13μm, 0.09μm and 0.065μm), finding that thinner oxides and shorter channel lengths can produce faster transistors. Analog baseband (ABB) and radio frequency (RF) designers are following suit, seeking an integrated approach to provide single-chip wireless solutions to their end customers.

However, voltage scaling does not keep pace with transistor scaling, which results in system solutions with significant leakage, which in turn reduces battery life. Fortunately, there are power management techniques that can reduce power consumption in single-chip solutions.

There are three forms of power loss that can be identified: active current consumption, standby current consumption (sometimes referred to as sleep mode), and leakage consumption in off mode. In active mode, power consumption is the sum of static bias current power consumption and average switching or clock (dynamic) power consumption. Standby is a low-power state because the clock has been gated or turned off, and almost all dynamic power consumption is zero. In this mode, the amount of static current determines the life of the battery. Finally, power consumption in off mode is a function of sub-threshold leakage. Subthreshold leakage refers to the current that the transistors in the chip have when the chip is turned off but the input voltage is still present.

If an ultra-deep submicron (UDSM) CMOS process can handle higher battery voltages (4.3V to 5.4V), the losses in the off mode will be negligible because the effective channel length will be longer and the gate oxide will be thicker. Likewise, the power consumption in the active mode will be less because the process is slow and frequency-aware, and the dynamic power consumption is a function of capacitance, frequency, and input supply.

Therefore, the DC battery power-up (DBH) problem of the power management circuit must be solved. The two most commonly used circuits that can achieve this after appropriate modifications are low-dropout regulators (LDOs) and DC-DC step-down switching regulators.

LDO Regulators

In a typical LDO design, most transistors are exposed to some input voltage, whether it is drain-source voltage (VDS), gate-source voltage (VGS), gate-drain voltage (VGD), gate-body voltage (VGB), or other combinations of the above. Therefore, for a simple design, the device's rated voltage must be at least equal to the battery voltage. For example, in 1.5V CMOS, the maximum voltage should be 1.8V.

Recently, process advances have allowed the inclusion of a drain extension on a conventional core transistor without increasing cost. This allows the VDS and VGD of a typical NMOS or PMOS core transistor to scale to higher voltages, but it does not increase the VGS value. Therefore, in a conventional design, if a battery connection is to be attempted, the device size must be focused and the current clamp must be used to extend. We cannot gain the full ultra-thin package benefits from future UDSM process nodes with this design because the geometry of the drain extension transistor cannot be shrunk as much as the core transistor.

One solution is to self-regulate a circuit around a pair of PMOS cascaded current mirrors. Using this technique, most core circuits can tolerate the battery voltage, assuming there is negative feedback to regulate or clamp the voltage at the input of the power supply circuit. For a PMOS LDO, this technique uses feedback within the LDO to regulate the LDO error amplifier at the core voltage.

The main DC/DC converter blocks connected to the battery are the output driver and level converter - the pre-driver. The output driver of the switching regulator can use a cascaded drain extended PMOS (DEPMOS) device and a high voltage gate (HVG, -1.8 V) PMOS device to implement the high-side switch. The low-side switch or synchronous rectifier can use a cascaded drain extended NMOS (DENMOS) device and a core (1.3V ~ 1.5V) NMOS device.

The advantages of using this cascade structure are that it allows high voltage operation, better leakage performance and smaller gate-drain capacitance, which must be switched if a single DEPMOS device is used. Since the battery is connected to a HVG PMOS device (whose maximum VGS is much smaller than VBAT), the VGS of both devices require protection schemes. The designer also needs a circuit to generate a constant voltage PBias, whose value is referenced to the battery voltage.

The PBIAS voltage can be set so that VBAT-PBIAS is less than the maximum VGS value of the transistor. The cascaded DEPMOS uses PBias as the bias voltage, and the voltage of the level shifter/pre-driver is between VBAT and VBAT-PBias when driving the HVG PMOS device. The level shifter/pre-driver can be designed in the same cascade as the output field effect transistor (FET).

Low Dropout Regulator

Integrating an external system pre-regulator in high-performance ultra-deep submicron CMOS and then breaking it into several smaller internal regulators can minimize the area consumed by this integration. Achieving higher transistor drive current per unit area can reduce the size of the pass FET. In addition, some of the more stringent analog and RF specification constraints only apply to one or two LDOs.

For example, a 100 mA LDO can be split into a 50 mA digital LDO, a 10 mA RF LDO, and a 40 mA analog LDO. For the digital LDO, power supply rejection and accuracy are not important, so the power FET can be reduced to the edge of the linear region. The analog LDO with a 40 mA load current becomes easier to compensate. It can be designed with high power supply rejection and its output pass FET operates at the edge of the linear region.

When using several LDOs, the quiescent current in standby mode will increase. For example, disabling the analog and RF LDOs in standby mode can reduce a considerable portion of the quiescent current. The remaining digital LDO consumes only 50mA to 250mA in an external solution.

One solution is to use an adaptive bias LDO design. The principle of this design is to positively feedback a portion of the output load current into the tail current of the differential pair of the LDO error amplifier, so the total quiescent current will only increase when the load current increases. This architecture can achieve a standby current of less than 10mA while still providing 50mA of output current and maintaining good transient load regulation.

DC-DC buck converters are used in higher current (greater than 200mA) applications where the LDO's reactive power becomes a significant portion of the total power. At full load, buck converters can achieve 95% of their reactive power, making them very attractive, but at the expense of larger area and more external components.

To maximize battery life, DC-DC converters must maintain high efficiency over a wide load range. Pulse width modulation (PWM) is used for high current loads, while pulse frequency modulation (PFM) mode is used for light loads. At high load currents, controlling the duty cycle of the PWM signal regulates the output voltage.

In PWM mode, the converter operates at a fixed frequency that can be filtered for noise-sensitive applications. In this mode, the main losses are conduction losses and switching losses that occur when the converter performs power conversion. In order to maintain high efficiency at light loads, the switching frequency should be reduced according to the law of PFM and allowed to vary with the load, thereby reducing switching losses. In addition, PFM mode can also shut down most of the circuit to reduce quiescent current.