High performance combined with a revolutionary breakthrough in size, weight and power consumption

Introduction

Today’s complex radar and avionics systems require high processing performance, but are faced with small size, weight and power (SWaP) constraints. The functions that drive these systems are signal processing intensive, so they can benefit greatly from the efficient implementation of digital signal processing (DSP) algorithms executed on small, high-performance, low-power processors. In addition, these systems have ever-increasing design and data usage requirements. To meet the SWaP efficiency and adaptability requirements, programmable DSPs and system-on-chip (SoCs) have become the processing platform of choice. They provide unparalleled signal processing capabilities at very low power for radar and avionics, as well as software-defined radio (SDR), imaging and video applications that often accompany radar and avionics.
Meeting the growing demand for SWaP efficient SoCs is not an easy task. This requires both high performance at a low cost and low power consumption to achieve operational and environmental goals. KeyStone-based multicore devices from Texas Instruments (TI) are the key to achieving SWaP efficiency. They provide multicore implementations of TI's leading TMS320C66x DSP cores, delivering the lowest power per watt in a small package. KeyStone devices are available in different performance levels with software compatibility across the family. This allows for diverse requirements, future-proofing the design and efficient development.
TI's TMS320C6657 and TMS320C6655 devices in the KeyStone platform are ideal for radar and avionics systems. These devices are pin-compatible single-core and dual-core KeyStone DSPs, respectively.

Fixed-point and floating-point processing
The use of multiple digital signal processor (DSP) cores is a key technology to enable waveform-intensive applications with increasingly complex signal processing techniques, such as avionics, radar, sonar, signal intelligence (SIGINT), image and video processing, and software-defined radio. Multicore capabilities combine a growing range of AccelerationPacs with development tools for multicore DSPs to deliver high performance at very low performance per watt in a compact package.

Avionics, radar and related applications require multicore DSPs to meet the increasing demands of these mission-critical applications, including higher processing throughput, finer resolution, higher precision and integration of advanced I/O. Many of these functions rely on floating-point math to achieve the required precision. TI's KeyStone architecture provides designers with a high degree of design flexibility by providing floating-point or fixed-point execution within a single device on an instruction-by-instruction basis. Floating-point operations are executed at clock rates up to 1.25 GHz, a rate typically only achieved with fixed-point devices. Designers no longer have to sacrifice performance for floating-point precision or design with separate fixed-point and floating-point processors.

Key Features

AccelerationPacIn

addition to excellent DSP performance, the C6657/55 also features Viterbi and Turbo AccelerationPacs, which can process communication and waveform algorithms in low-power hardware while fully utilizing the 1MB L2 memory and 1MB shared memory per core. These AccelerationPacs can run independently of the programmable cores, freeing up DSP resources for other processing, thereby reducing latency and optimizing software development. The KeyStone architecture's Multicore Navigator provides a hardware-based abstraction layer that frees software developers from the detailed tedious work of low-level hardware design. The Multicore Navigator's queues and descriptors can be used to automatically point software tasks to the appropriate resources, making scalability and resource pooling an integral function of the processor. Software using the Multicore Navigator can run on any KeyStone device, providing scalability from one DSP core to multiple DSP cores without changes. These factors combine to provide the low-power high performance required for SWaP-oriented applications. C6657/55 uses 40nm process technology and can provide up to 80GMAC and/or 40GFLOP performance at 1.25GHz. Figure 1 is a functional diagram of C6657. Figure 1


: TMS320C6657/55 block diagram

High-performance I/O

In general, these systems need to interoperate not only with devices from multiple vendors, but also with other legacy systems. C6657/55 provides a high-performance peripheral set that supports the high data transfer rates required by modern systems and has high flexibility to support legacy designs. These peripherals include:

dual-lane PCI Express ports supporting GEN2 up to 5GBaud per lane;

4-lane Serial RapidIO® (SRIO) compliant with the RapidIO 2.1 specification supporting up to 5Gbps per lane;

HyperLink for resource expansion supporting up to 50GBaud interconnect with other KeyStone architecture devices;

Gigabit Ethernet (GbE) ports with an SGMII port supporting up to 1000Mbps;

32-bit DDR3 with an ECC interface supporting up to 1,333MHz;

16-bit external memory interface (EMIF) for connecting to flash memories (NAND and NOR) and asynchronous SRAM;

8-bit or 16-bit dual-channel universal parallel port, with each channel supporting SDR and DDR transfers; and

2 multi-channel buffered serial ports (McBSP).

The C6657/55 takes full advantage of the rich peripherals and AccelerationPac in the KeyStone architecture to achieve full multi-core benefits in a compact form factor and low power.

SRIO, PCIe and HyperLink enable high-speed interconnects between multiple SoCs and/or FPGAs. HyperLink is an interface extension of the internal bus of the KeyStone architecture, providing 50Gbps in point-to-point high-speed interconnects. HyperLink provides a low-overhead protocol that supports high-speed communication and connectivity with other KeyStone devices or FPGAs. It provides a solution that meets the scalability requirements of current radar, SDR and avionics systems. However, SRIO and PCIe enable interconnects based on various standards at lower bit rates.

The 32-bit DDR external memory interface in the C6657 (with ECC) provides a 1,333MHz bus that supports 8GB of addressable memory space. TI DDR3 implementation reduces the latency associated with external memory accesses, providing the necessary support for the large amounts of data associated with running these applications at high speeds.

Size and power

SWaP are the main requirements for these mission-critical applications. TI has long been committed to providing the industry's lowest power DSP and SoC. The C6657 not only supports dual C66x DSP functions, consumes less than 3.5 watts at 1GHz, but also provides an ideal combination of performance and peripherals to meet market needs. The compact 21x21 mm package meets the small form factor requirements of mission-critical applications. The C6657/55/54 devices also offer the latest "ultra-thin" package (only 2.9 mm thick) to optimize the overall system-level packaging requirements of mission-critical applications. In addition, these devices also support a wider operating temperature of -55 to 100C, which is usually required for avionics applications.

In addition, the C6657 can also support the most complex waveforms in software-defined radio. VCP and VCP3d accelerators, internal shared memory (up to 3MB) and interface bandwidth provide the necessary high performance to support and generate the most complex waveforms used in many SDR applications.

Radar Design Requirements

Modern radar designs incorporate signal processing functions in the front end (exciter/receiver) of the radar system. These may include waveform generation, filtering, matrix inversion operations, and signal correlation. In addition, radar systems require mathematical functions including recursive least squares and square root operations. Many designers implement these functions in C-based processors (using fixed-point decimal and/or floating-point operations). These types of designs can take advantage of the small dual fixed/floating-point cores available in TI's C6657 to meet system requirements.

For example, matrix inversion is an important factor in adaptive array design and standard spatial transceiver array processing (STAP). Matrix inversion can reduce latency and system power consumption depending on the size of the array used in the radar system by taking advantage of the parallel processing capabilities provided by the C6657 DSP. As the size of the array in the system increases, the number of floating-point multiplications required also increases. The most feasible design approach for radar system designers is to implement this function using the DSP and internal memory blocks. The C6657 offers up to 40 GFLOPs of performance and 3MB of internal memory, making it an ideal choice for this application.

ConclusionTI

C6657/55 DSP integrates peripherals and processing functions to provide many advantages for system design, including fixed-rate floating-point performance, higher system flexibility, and lower system cost and power consumption. The peripherals integrated on the device provide network connectivity (EMAC), high-speed memory interfaces with ECC support, standard bus interfaces (PCIe), and high-speed, low-latency point-to-point interfaces (HyperLink). This advanced peripheral set enhances system performance and scalability, and combined with high integration, further reduces system cost. The C6657/55 integrates fixed- and floating-point digital performance to provide unique advantages when running complex, computationally intensive algorithms required by radar, SDR, and avionics applications.

In summary, the TI C6657/55 DSP not only provides excellent SWaP performance for mission-critical applications, but also reduces chip count and board space for the overall system.