Amplifier Leakage Current Analysis

Have you ever spent a lot of time selecting the best op amp for your circuit only to find out that the offset voltage at the manufacturer's reference input is wrong? What if in your application circuit you find it is 10 times the specification? Do you send the chip in for failure analysis or throw it away and look at your amplifier list again? As a solution, I suggest that you account for the compensation error by re-examining your amplifier's specifications.

If you use an amplifier as a critical component in a transimpedance amplifier, analog filter, sample-and-hold circuit, integrator, capacitive sensor, or any other circuit where you have high impedance components surrounding your amplifier, you may find that the amplifier’s input bias current creates an offset voltage error in the resistance of your circuit.

In the days of bipolar amplifiers, the term “input bias current” was an accurate description, and it is still true today. The input bias current of a bipolar amplifier is the same as the base current of an NPN or PNP transistor at the input of the amplifier. The magnitude of bipolar amplifier input bias current ranges from a few nanoamperes for low power devices to hundreds of nanoamperes for high power devices.

The term “input bias current” loses its meaning when you look at JFET or CMOS input amplifiers. With these types of amplifiers, the current pulled or sunk from the amplifier input pins is actually the leakage current of the input ESD (electrostatic discharge) cell (see Figure 1).

Figure 1 Input bias or leakage current generates voltage drop across Rp

A more accurate description of this current error would be “input leakage current.” A JFET or CMOS amplifier has leakage current of less than 1 pA at 25°C. This specification is independent of common-mode voltage and amplitude amplifier power. Almost all amplifiers have ESD cells for protection from ESD events, but you will never see ESD leakage current in a bipolar amplifier. The input bias current exceeds the ESD cell leakage current of a few microamperes.

Input bias and input leakage currents vary with temperature. However, depending on the op amp design, bipolar input bias currents can be very stable. However, this may not be the case with JFET and CMOS input amplifiers. Since leakage currents come from reverse biased ESD diodes, leakage currents increase by about a factor of 2 for every 10°C change in temperature.

In ensuring that input leakage remains as low as with JFET and CMOS amplifiers, you must understand the effect your PCB (printed circuit board) has on picoamp currents. For example, small amounts of dust, oil, or water molecules can increase leakage and masquerade as input bias current. But if you take extra care, you can build a PCB that meets the 1-pA performance specification.

The most effective way to reduce or minimize input bias or input leakage current is to examine your circuit structure. As you examine your circuit, look at the voltage characteristics of each node and make sure you understand the impact of all current paths in your circuit.