Introduction of a New Method for Current Detection in Switching Regulators

0 Introduction

As electronic products develop towards miniaturization and portability, monolithic integrated high-efficiency, low-power-voltage DC-DC converters are widely used. Current detection circuits are used in many power management ICs.

In a current mode PWM controlled DC-DC converter,

Where: μ is the channel carrier mobility; Cox is the gate capacitance per unit area; VTH is the turn-on voltage of MOSFET.

As shown in Figure 1, given the equivalent resistance of the MOSFET, the switching current can be detected by detecting the voltage between the drain and source of the MOSFET.

This technology is perfect in theory, it does not introduce any additional power loss, does not affect the efficiency of the chip, and is therefore very practical. However, this technology has a fatal disadvantage of low detection accuracy:

(1) The RDS of MOSFET itself is nonlinear.

(2) Whether it is the MOSFET inside or outside the chip, its RDS is greatly affected by μ, Cox, and VTH.

(3) The RDS of MOSFET changes exponentially with temperature (the change is 35% from 27 to 100°C).

It can be seen that this detection technology is greatly affected by the process and temperature, and its error is between -50% and +100%. However, because the current detection circuit is simple and does not consume any extra power, it can be used in situations where the current detection accuracy is not high, such as overcurrent protection of DC-DC regulators.

[page] 1.2 Using Sense Field Effect Transistor (SENSEFET)

This current detection technology is quite common in practical engineering applications. Its design idea is: as shown in Figure 2, a current detection FET is connected in parallel at both ends of the power MOSFET, and the effective width W of the detection FET is obviously much smaller than that of the power MOSFET. The effective width W of the power MOSFET should be more than 100 times that of the detection FET (assuming that the effective lengths of the two are equal, the same below), so as to ensure that the additional power loss caused by the detection FET is as small as possible. The currents of nodes S and M should be equal to avoid the inaccurate current mirror caused by the FET channel length effect.

When the potentials of nodes S and M are equal, the current IS flowing through the detection FET is 1/N of the power MOSFET current IM (N is the ratio of the width of the power FET and the detection FET), and the value of IS can reflect the size of IM.

1.3 Combination of Sense Field Effect Transistor and Sense Resistor

As shown in Figure 3, this detection technology is an improved form of the previous one, except that its detection device is not FET but a small resistor. In this detection circuit, the resistance value of the small resistor is much more accurate than the RDS of the detection FET, and its detection accuracy is relatively higher. In addition, there is no need for a special circuit to ensure that the voltage at the drain end of the power FET and the detection FET is equal, which reduces the design difficulty. However, the cost is that the additional power loss caused by the detection of the small resistor is smaller than 1/N2 of the first detection technology (N is the ratio of the width of the power FET to the detection FET).

The disadvantage of this technology is that, due to the unequal VDS of M1 and M3 (considering the influence of VDS on IDS), the ratio of IM to IS is not strictly equal to N, but this deviation is relatively small. In engineering, N should be as large as possible and RSENSE should be as small as possible. This detection technology can be used in high-efficiency, low-voltage output, and large-load application environments.

[page] 2 New current detection method

In FIG4 , N_DRV is the synchronous tube gate drive signal of the BUCK regulator, N_DRV_DC is the DC component filtered out by N_DRV after passing through a third-order RC low-pass filter, and the DC component is input to one end of the comparator, and the other end of the comparator is input to a reference voltage value BIAS, and the output LA28 (digital signal, output to the control logic of the chip) of the comparator is a DC-DC load current state detection signal.

In a voltage regulator chip, there is both a DC-DC (BLYCK) and an LDO. It works in PWM mode under medium and heavy loads, and works in LD0 under light load (about 3 mA or less). The function of the current detection circuit proposed in this article is: when its load current is less than a certain value (at this time the switching regulator is in DCM mode), the LA28 level jumps to realize the mode switching from PWM mode to LD0 mode.

It should be noted that if the output load current is detected directly or by taking the average value of the inductor current, it will bring difficulties in circuit implementation. However, the detection method proposed here does not have this problem.

This architecture diagram is an equivalent diagram of the DC-DC load current state detection circuit. Its function is that when the DC-DC load current is lower than 3 mA, its output signal LA28 changes from high to low, thereby realizing the switch from PWM mode to LD0. Its basic principle is to use the relationship between the load current and the switch gate drive signal N_DRV in DCM mode (when the load current is 3 mA, the DC-DC is in DCM mode), and monitor the change of the output load current by detecting N_DRV, so as to realize the switch from PWM mode to LDO when the load current is lower than 3 mA.

FIG5 is used below to illustrate the principle of the circuit for detecting load current.

FIG. 5 is a waveform diagram of the inductor current IL and the synchronous transistor gate drive signal N_DRV in the DCM mode.

In this figure, the rising slope of the inductor current is

, and the downward slope is

, then:

and

[page] At this time:

Since the amount of charge output to the load through the inductor in each cycle is constant, we have

Where: T is the switching period; IOUT is the output load current.

From the above formulas we get:

Therefore, there are:

Now let’s analyze Figure 4 again. In the frequency domain, the system transfer function from N_DRV to N_DRV_DC is:

Therefore, the network composed of R and C in Figure 4 is a third-order RC low-pass filter. Next, we calculate N_DRV_DC. From t=0, we connect a periodic rectangular pulse signal N_DRV with a pulse width of △T and a period of T. Its image function in the complex frequency domain is

.

Therefore, the image function of N_DRV_DC is:

It should be noted that when designing a third-order RC low-pass filter, its bandwidth should be set much smaller than the DC-DC oscillator frequency (i.e., the frequency of N_DRV) to ensure that the high-frequency components in N_DRV are well filtered out; but it should not be set too small, otherwise the resistance and capacitance used will be relatively large.

[page] When the DC-DC load current decreases, N_DRV_DC will also decrease. If it decreases to N_DRV_DC=BIAS3, the comparator starts to change from high to low, and the chip will enter LD0 mode from PWM mode. Assume that the load current at this time is ILDO(ON), then:

Right now:

Combining equation (1) and equation (2), we get:

The final current detection implementation circuit is shown in Figure 6. Since the circuit principle is relatively simple, the analysis is omitted.

3 Simulation results data

The simulation results are shown in Table 1. TA = 25 ° C, L = 2.2 μH.

4 Conclusion

A new method for current detection of switching regulator is proposed . By detecting the synchronous tube gate drive signal in DCM mode, the output load current is detected, so as to obtain the switching of the chip from PWM mode to LDO mode. This solves the difficulty of circuit implementation by detecting the average current of the inductor. After HSpice simulation verification, it only consumes 5μA of static current. This detection method is mainly suitable for occasions where the load current of the switching regulator in DCM mode needs to be detected.