Design of Control Power Supply for Plasma Display Panel (PDP)

introduction

As people's demand for large-screen color TVs continues to increase, plasma displays (PDPs) have a considerable advantage in the competition due to their unique advantages such as small size, wide viewing angle, active luminescence, high brightness, and good environmental adaptability. As prices decrease, they will surely enter households and have huge market demand. Plasma displays are mainly composed of display screens, shielding glass, power supplies, digital circuits, drive circuits, and shells. The power supply is responsible for the power supply of all circuits in the screen and the display screen. It has high technical content and complex functions. In order to meet the safety requirements of plasma displays, careful design and strict testing are required.

Power output characteristics

In order to adapt to the global input voltage range, the AC input voltage is 85~276V. After EMI filtering and rectification, active PFC is used for voltage pre-adjustment. There are 8 output voltages: address drive power supply Va, screen drive power supply Vs, logic control power supply Vcc, auxiliary power supply (3 channels), fan power supply, standby power supply Vsb. Its main output characteristics are as follows:

Screen drive power supply (Vs) output: 165~185Vdc (controllable), automatically set, Vs=165+10×Vrs, Vrs is the reference voltage, between 0~2V, provided by PDP, the average current Is is 1.5A, the instantaneous maximum current Isp is 12.0A;

Address drive power supply (Va) output: 55~65Vdc (controllable), automatically set, Va=55+5×Vra, Vra is the reference voltage, between 0~2V, provided by PDP, the average current Ia is 1.8A, and the instantaneous maximum current Iap is 3.0A;

Logic circuit power supply (Vcc) output: 5Vdc (controllable), instantaneous maximum current Icp is 5.0A; auxiliary power supply output: +5V, 3.5A; +12V, 1A; -5V, 0.5A; 12V fan power supply (Vfan): current is 0.5~1.0A; 5V standby power supply (Vsb): current is 0.5~1.0A.

The address driving power supply Va and the screen driving power supply Vs are controlled by the PDP respectively, and there are timing requirements, so two independent DC/DC converters are used; for the standby power supply Vsb, it still works when the PDP is not working, that is, when all other outputs are turned off, so Vsb uses an independent DC/DC converter; Vcc is common to Vs and Va. To avoid interference on the ground line, the auxiliary power supply group uses a separate group of DC/DC converters, and the output is internally common. At the same time, in order to avoid differential frequency interference, the high-power Va and Vs converters use a frequency synchronization working mode (synchronized with the PFC circuit). The logical relationship and working sequence of each converter are as follows:

a. After AC power is turned on, the standby power supply Vsb starts working;

b. After the remote control is turned on, the relay is first closed, the PFC outputs a DC voltage, and the auxiliary power supply and PDP logic control power supply Vcc work;

c. After the screen control circuit is initialized, it sends a startable high-voltage drive start level Vrr to the PDP power supply, Va and Vs start working;

d. When the remote control is turned off, the screen control circuit turns off Vs and Va first, and then turns off Vcc and auxiliary power supply;

e. After the remote control is turned off, the standby power supply still works for the next startup.

The power on and off timing sequence is shown in Figure 1(a) and (b).

(a) Power-on sequence

(b) Shutdown sequence

Figure 1 Power on/off timing diagram

In Figure 1, t1 is the start-up delay between the high and low voltages inside the PDP power supply, which is about 110ms. Vrr is a high voltage blocking signal. After Vrr is at a high level, there is a high voltage output. In the figure, t3 represents the soft start time of Vs (165V), which is about 300 to 800ms, while Va (65V) has no soft start. t4 and t5 only represent the order of shutdown. The value of the value itself is closely related to the load. Under full load, t4 is about 450ms and t5 is about 260ms. Vs and Va converters are started and shut down together. When one of the two current circuits is protected (overcurrent, overvoltage, overheating), the two converters are all shut down, but the Vcc converter is not shut down. When the Vcc converter fails, the Vs and Va converters are shut down at the same time as the Vcc converter. The structural block diagram of the entire power supply is shown in Figure 2.

Figure 2 Structure diagram

Circuit Design

In order to meet the above-mentioned characteristic requirements of the PDP power supply, each power supply requires a different circuit structure. The design of each circuit is discussed in detail below.

EMI circuits, active power factor correction circuits and standby power supplies

In order to meet the needs of globalization, PDP power supplies must meet the EMI test requirements of various organizations. Based on impedance matching, an EMI filter with a topology structure as shown in Figure 3 is used. After parameter optimization and PCB optimization, its conducted radiation passes the CLASS B standard. The active power factor correction circuit uses UC3854 as the main control chip, and the power factor reaches 99%. The standby power supply uses PI's dedicated standby power supply chip to form a single-ended flyback converter.

Figure 3 AC input filter circuit topology

Auxiliary power supply

The auxiliary power supply uses UC3844 to form a single-ended flyback converter, with voltages of 5V/3.5A, -5V/0.5A, 12V/0.5A, 12V/1.0A, and 5V master control.

Address driving power Va and screen driving power Vs

The power of these two power supplies is relatively large and controlled, so two independent dual-tube dual forward converters with the same structure are used. We take the address drive power supply Va as an example for design. The power of this power is 120W, and the output is 55~65Vdc (controllable). It is automatically set, Va=55+5×Vra, Vra is the reference voltage, between 0~2V, provided by PDP. When Vra is 2V, the corresponding output of Va is 65V. Its control circuit uses the SG3525 chip, and the Vra voltage is added to the 1st pin of SG3525 after voltage division and filtering to control the output voltage. The main topology uses a dual-tube dual forward converter, which is characterized by low device stress, no residual magnetism problem, simple circuit, and avoidance of direct-through problem. Figure 4 is the principle circuit of the dual-tube dual forward converter.

Figure 4 Principle circuit of dual-switch dual forward converter