From high frequencies to low frequencies, IBIS is everywhere

One challenge facing high-speed digital designers is dealing with overshoot, undershoot, mismatched impedance ringing, jitter distribution, and crosstalk on their boards. These issues all fall under the umbrella of signal integrity. Many high-speed designers use the Input/Output Buffer Information Specification (IBIS) modeling language to anticipate and address signal integrity issues. This modeling language has been in widespread use since the 1990s and has evolved into a formal standard: EIA-ANSI 656-B. The 5th edition of the standard, published by the IBIS Forum in August 2008, remains prevalent. IBIS uses current-voltage (IV) and voltage-time (Vt) data tables to describe the characteristics of a device's I/O pins. Vendors generate these tables by simulating or measuring their device's I/O cells.

For high speed designs that are now clocked at up to 20 Gbits/sec, I can understand the need for this type of system simulation tool. IBIS makes the SPICE simulation option less important because simulation times are much shorter with the same accuracy. When I say IBIS simulation times are shorter, I mean that a transistor-level SPICE simulation can take minutes or hours to perform for a large PCB system, as opposed to days or weeks. With a single IBIS simulation, you can generate many transmission line responses and eye diagrams.

The IBIS format has proven its value in the industry for high-speed applications. However, what really surprises me is that customers are now asking for IBIS support for lower frequency devices (e.g., clock devices below 40 MHz). Initially, I thought that component engineers had been trying to standardize their calibration tables. Now, I am not so sure. Even at lower frequencies, we face many signal integrity issues due to digital signal edge rates. These fast edge rates are responsible for ringing clock signals, causing misinterpretation of a command or even an ADC burst 2 gain. IC manufacturers have very mature SPICE simulation macro models for precision devices, but they are following our IBIS digital I/O model library. Figure 1 depicts an example where an IBIS model simulation is very effective.

Figure 1: ADC processor clock signal (CH3) and data signal (CH12) to the ADC on the processor.

In Figure 1, the designer paid no attention to the line impedance. This figure shows the measured results of the ADC in the system. The ADC and processor are on their own boards, and the designer simply connected the two boards together with a 1-meter long CAT-5 twisted pair cable. In Figure 1, the processor's clock signal frequency (CH3) is 2.25 MHz. The ADC uses this signal to synchronize data transmission back to the processor (CH2).

Initially, designers thought that the slow clock speed between the two devices would not cause termination problems. However, the clock and data signal termination method creates many signals that exceed the specified high and low thresholds (overshoot and undershoot), have false edges (ringing), and reduce operating margins (weakened eye diagrams).

IBIS simulation to the rescue! Save time and reduce costs before you implement your circuit into hardware. Vendor-provided IBIS models, as well as models of your board, are useful things to have in your toolbox when you simulate a design before prototyping. Signal integrity issues can affect both your high-speed and low-speed systems. Using simulation circuit analysis at an early stage, you can impose many different conditions on your system to prevent and detect common signal integrity issues.