Serial interface for high speed ADC

In medical applications such as magnetic resonance imaging (MRI), ultrasound, CT scanners, digital X-ray, etc., it is often necessary to use analog-to-digital converters (ADCs) with many channels to sample a large amount of data. Using a serial interface to obtain the sampled data reduces the pin count of the ADC and the FPGA. In addition, high-speed serial interface routing saves board space. Since board resources are scarce and FPGA pins are also very valuable resources, the advantages of serial data converter interfaces compared to parallel interfaces are obvious. Today, there are two serial interfaces available for high-speed data converters. The first option is the serial clock-data-frame (CDF) interface, which combines a serialized LVDS (low-voltage differential signaling) data stream with a differential clock and a frame clock, where the differential clock is used to accurately collect data and the frame clock is used to establish the edge for data sampling. The second option is to use the JESD204 standard, in which the clock is embedded in the high-speed two-wire serial data stream at the Gbps level. Both interfaces have their own advantages and disadvantages. Since the current mode logic (CML) pairs used to drive the high-speed JESD204 interface require a lot of power, serial LVDS is the preferred choice for low-power portable designs with a large number of channels. However, in situations where serial LVDS is not suitable, the JESD204 interface can play a role.

Advantages of Serial LVDS
The serial LVDS output format reduces the number of digital I/Os required between the ADC and the FPGA, saving FPGA pins, board area, and cost. In addition, by using a serial interface on the data converter, the number of pins required on the data converter is greatly reduced, allowing for a much smaller package size. This advantage is particularly evident in designs with many channels. The decision to use a serial LVDS interface versus a parallel interface depends on whether the application can tolerate more power and whether the FPGA is capable of handling the high-speed data stream. The LTC2195 is a 16-bit, 125Msps dual-channel ADC with serial LVDS outputs that consumes only 216mW per channel. However, the serial LVDS interface consumes 31mW more per channel than the LTC2185, a dual-channel parallel output version (see the full product line diagram in Figure 1). This 16-bit high speed ADC family offers excellent 76.8dB baseband SNR performance and 90dB SFDR while consuming very low power when using a 1.8V supply.

Figure 1: Linear Technology's 16-bit low power, high speed ADC family

For high-speed ADCs, when coordinating the data clock, frame clock, and data, both the transmitter and receiver typically require a phase-locked loop (PLL) to properly coordinate the data clock. At GHz rates, this coordination is very difficult, and the data rate is primarily limited by the receiver. Ultimately, above 1GHz, this 6-wire serial transmission method is generally not used, limiting the ADC rate or the ADC resolution.

For a 16-bit high-speed ADC, this limits the sampling frequency to 62.5Msps. To achieve higher sampling frequencies, two or four "lanes" can be used per ADC channel. When using two "lanes", the serial data rate is halved, and the odd and even bits are separated into two serial data stream differential pairs. When using dual "lane" mode, a 16-bit 125Msps ADC will provide a serial output data rate of 1Gbps. The LTC2195 serial LVDS family offers an additional 4-lane mode, allowing for a much lower data rate of 500Mbps, using 4 differential pairs per channel for a total of 20 lines, including the differential frame and clock pairs (see Figure 2). This allows interfacing with lower-priced, lower-speed FPGAs. To put the number of digital output lines required into perspective, consider the case of parallel LVDS outputs, which would require 32 lines per channel. Today, ADCs are available with dual data rate (DDR) LVDS outputs that require only 16 lines per channel. With such devices, the data rate at the output is twice the sampling frequency. Dual 16-bit ADCs such as the LTC2185 also offer optional DDR CMOS outputs, which reduces the number of required data lines to just 8 per channel. When considering single-channel high speed ADCs such as the 16-bit, 125Msps LTC2165, it no longer makes sense to provide a serial LVDS interface, as there is no difference in the number of data lines required. DDR CMOS uses eight parallel output lines, while two-lane serial LVDS (required due to sampling rates above 62.5Msps) also uses eight lines (four for data and four for data clock and frame clock). In addition, serial LVDS increases the power consumption of the device, which is a concern for portable applications.

Figure 2: Digital output configuration of the 16-bit low-power ADC family

For high channel density medical applications, Linear Technology now offers an 8-channel 14-bit 125Msps ADC LTM9011-14. This new low-power device uses a compact 140-pin 11.25mm x 9mm BGA package and provides 73.1dB signal-to-noise ratio (SNR) performance and channel isolation greater than -90dBc. For optimal performance and to save space, the device also integrates all necessary bypass capacitors close to the chip. At 125Msps, the power consumption is only 140mW per channel. The 80Msps (LTM9009-14) and 105Msps (LTM9010-14) versions consume 94mW and 113mW per channel respectively, and lower sampling rate, lower power versions are under development. For portable applications, the LTM9011 series provides a sleep mode that can reduce power consumption to only 2mW. The LTM9011 is available in serial LVDS format and offers a dual “lane” output mode for sampling rates above 62.5Msps. The LTM9011 8-channel family is based on the low power, 14-bit and 12-bit, 25Msps to 125Msps serial LVDS 4-channel (LTC2175) and dual-channel (LTC2268) ADC family with similar performance characteristics (see Figure 3). New U.S. Export Administration regulations have changed the classification of these devices, and the Export Control Classification Number (ECCN#) for these devices has been changed from 3A001 to the less stringent ECCN# 3A991. These devices offer unmatched performance at ultra-low power consumption of just over 1mW per Msps, maintaining portability for many medical applications. For a complete list of high speed ADC products not subject to U.S. export control regulations, please visit: www.linear.com.cn/hsadc_nolicense.

Figure 3: 14-bit/12-bit, 25Msps to 125Msps quad/dual ADC family with serial LVDS outputs

Digital designers are perhaps all too familiar with the challenges of routing high-speed digital lines between ADCs and logic devices. Designers must be extremely careful to ensure adequate spacing between high-speed traces and to ensure that digital signals do not cross analog boundaries. Poor layout can cause digital switching noise to feed back into the analog inputs of the ADC, degrading overall system performance. The LTM9011 family offers a pass-through pinout configuration that reduces the board area required to route data I/O lines and simplifies layout, minimizing issues related to digital feedback (see Figure 4). Other options include a data output randomizer to reduce digital feedback, seven programmable LVDS output current values, internal 100Ω LVDS output termination resistors, and digital output test patterns. These configurations can be easily set through SPI or hardwired to achieve a smaller set of operating modes.

Figure 4: 14-bit, 80Msps to 125Msps, 8-channel ADC provides pass-through pinout
for easy routing to the FPGA

All of these serial LVDS ADCs from Linear Technology can be evaluated using a demo board equipped with a VITA-57 FPGA Mezzanine Connector (FMC). Engineers can also evaluate the performance of multiple parallel input channels using the powerful PScopeTM QuikEvalTM II software. PScope software is Linear Technology's high-speed ADC evaluation software. For a simple program, it completes complex calculations in seconds. PScope software enables engineers to quickly and easily evaluate signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), total harmonic distortion (THD) and other key parameters of high-speed ADCs. The PScope tool can also perform more complex calculations, such as calculating intermodulation distortion for two single-tone tests, or calculating the adjacent channel power ratio (ACPR) of a spread spectrum signal at the push of a button. It also supports multi-channel ADCs such as the LTM9011, allowing 8 ADC channels to be measured simultaneously.

Figure 5 is a screenshot showing the power of the PScope data collection and analysis software tool.

Figure 5: Linear Technology’s PScope data converter analysis software

JESD204 High Speed ​​Serial Interface
8B/10B encoding was originally invented by IBM in 1980, which eliminates the need for frame clocks and data clocks, allowing single transmission line pair communication at serial data rates above 2GHz. The unique characteristics of 8B/10B encoding allow the data clock to be embedded in the data itself and maintained with the frame by the initial frame synchronization using the COMMA (comma) character. To implement this coded data converter interface in a standardized manner, the JEDEC specification JESD204 defines the required protocol and electrical characteristics, which has enabled a new generation of faster and more accurate serial ADCs, such as Linear Technology's 16-bit, 105Msps ADC LTC2274 with 77.6dB SNR and 100dB SFDR. The JESD204 interface takes advantage of the SerDes ports available on many high-performance FPGAs, freeing up general-purpose I/Os for other functions. The disadvantage is that the current mode logic drivers on the ADC consume much more current than LVDS drivers. Additionally, there must be enough SerDes ports available to accommodate all ADC interfaces.

Advantages over Typical 6-Wire Serial Transmission8B
/10B encoded data is suitable for clock recovery circuits because of its limited run length. In addition, because it is DC balanced, it can also accommodate AC coupling. 8B/10B encoding requires a conversion from an 8-bit group to a 10-bit code group. In each code group, the difference between the number of "1" and "0" never exceeds 2. By monitoring the number of "1" and "0" in consecutive code groups, a running difference can be calculated. The transmitter and receiver use this difference to encode and decode the data. For each input octet, there are two possible 10-bit output codes. Which code is selected for transmission depends on the running difference and aims to keep the average number of "1" and "0" equal. This characteristic of 8B/10B encoding ensures that the DC offset of the signal is zero. When data is encoded, it is serialized and transmitted (starting with the "0" bit of the first code group). The JESD204 specification requires that the first code group corresponds to the most significant byte of data. The second code group corresponds to the least significant byte of data. The two code groups are combined to form a data frame, which in turn constitutes a sample. A 16-bit ADC is encoded into two 10-bit code groups, which are then multiplied by the sampling rate to determine the bit rate of the two-wire serial data stream. The 16-bit 105Msps LTC2274 produces a serial data stream that transmits at 2.1Gbps after encoding. At this speed, 8B/10B encoding and its unique characteristics enable reliable transmission of serial data over a two-wire interface. The

JESD204 serial interface makes the most sense for cost-sensitive applications where the FPGA pin count determines the cost of the design. Multichannel applications such as medical imaging will benefit from the reduction in pin count due to ease of routing and additional space savings.

Conclusion
The choice between serial LVDS and the JESD204 interface standard will depend on the power requirements and availability of SerDes ports on the FPGA. If portability is a consideration, serial LVDS is best suited for multi-channel ADCs with sampling rates up to 125Msps and resolutions up to 16 bits.