Designing a Multi-Output Switching Power Supply Using a Secondary-Side Synchronous Switching Post-Regulator (SSPR)

At present, multi-output converters generally use closed-loop PWM control for the main output, while other auxiliary outputs use indirect voltage regulation. Since only the main output is closed-loop controlled, the change in duty cycle has a greater impact on the load of the auxiliary output, especially when changing from light load to full load, the performance of load cross-regulation deteriorates. Commonly used technologies are as follows.

First, the design of multi-output converters can consider a variety of topologies. Usually, the main output is adjusted, and the other auxiliary outputs are cross-adjusted according to the corresponding turns ratio of the isolation transformer. There are many problems with this method, including flyback and forward converters, especially in addition to adjusting the output voltage in the main circuit, it is very difficult to obtain accurate voltages at each auxiliary output, because the turns ratio used in the design of the multi-output power transformer is only an approximation. In addition, the transient load effect on any one output will be reflected on all other loads. And, due to the leakage inductance between the transformer windings, the load cross-regulation rate will be relatively poor. These problems can be solved by setting the cross-adjusted output voltage slightly larger than the required value and adding a linear regulator to each auxiliary output, as shown in Figure 1. When the current is less than 3.0A, it is best to use a linear regulator as the post-stage adjustment output, but this method will sacrifice greater efficiency at the expense of limiting low output current applications. If a multi-output flyback converter using WVC technology is used, the DC and transient characteristics of the output can be effectively improved. Specifically, each output voltage is sampled and weighted to adjust the duty cycle D. If the weighting coefficient and compensation link are designed reasonably, the power quality will be significantly improved. The multi-channel output of the forward converter adopts the design method of coupled inductor, which requires the turns ratio of the inductor to be equal to the turns ratio of the output winding of the main transformer. There is no significant improvement in the cross-regulation performance under the power consumption environment with asymmetric load.

Figure 1 Linear regulator

Second, in order to improve the load cross-regulation rate, separate DC/DC converters can be used to combine and achieve multi-channel output voltage regulation, but the circuit is relatively complex and very expensive. Another option is to use the UC3573 controller to design a buck converter as a post-regulator, as shown in Figure 2, which is more suitable for 3.0-8.0A current output. This method can achieve a high efficiency of 90%, but if the post-regulator uses multiple secondary coils, it is necessary to add rectifiers, inductors and capacitors. This method adds a first-level LC filter circuit, and the number of filters increases significantly when there are multiple outputs. At the same time, this buck chopper circuit is generally used in circuit structures with low input voltage and output voltage.

Figure 2 Buck converter

Figure 3 Magnetic amplification regulator

Third, the magnetic amplification post-regulator is designed with the UC1838 controller, as shown in Figure 3. It is highly efficient, especially for low and medium current applications greater than 5.0A, but is inefficient in high current applications. Moreover, it is not easy to implement over-current protection, the low regulation at light loads, and the high cost of the magnetic amplification inductor at high frequencies (200kHz) make it not a perfect solution.

Figure 4 Secondary-side synchronous post regulator

Fourth, a better choice is to use a new type of secondary-side synchronous post regulator (SSPR), as shown in Figure 4. This can achieve both leading and trailing edge regulation. SSPR has the advantages of simplicity, high efficiency, high frequency, lossless overcurrent protection and remote control switch in the precise regulation of multi-output isolated power supplies. The application of CS5101 is simpler than the control circuit of LM5115, UCC2540 and LT3710 with dual N-channel MOSFET post synchronous regulators, and can adapt to various circuit structures with high and low input voltages. CS5101 is a synchronous leading-edge switch regulation controller with N-channel MOSFET drive, which can directly generate a precisely regulated secondary output from the secondary winding of the transformer, thereby minimizing the size of the main output inductor and capacitor. At the same time, it can be applied to single-ended or double-ended topologies.

Description of Secondary Side Synchronous Post Regulator (SSPR) Operation
The SSPR regulator allows the secondary circuit to independently control the output without primary side feedback. The SSPR switch is followed by the secondary side rectifier diode and output inductor. In the current mode single ended forward topology, the primary controller maintains a stable volt-second value. The leading and trailing edge primary current waveforms are shown in Figure 5. In the case of current mode control leading edge using peak current measurement, trailing edge modulation will cause loop instability.
The CS5101 SSPR controller is designed as a leading edge modulation and is used in current mode or voltage mode control.

Figure 5 Main switch current waveform

Application of SSPR Technology
SSPR can be used in various circuit topologies, including single-ended/double-ended buck converters, flyback converters, and can be used in current control mode or voltage control mode.

Figure 6 Main switch waveform

In each topology, an N-FET power switch is typically used in series with a forward diode, as shown in Figure 6. Since the N-FET is connected between two diodes, it is not possible to use a single common cathode or common anode rectifier, and the source voltage of the N-FET varies from the transformer secondary peak voltage to approximately -0.7V (the forward voltage drop of the reverse diode), and the designer must create a floating driver ground.

Figure 7 Main switch waveform when the filter inductor is at the ground end

If the transformer's secondary multi-channel output does not need to be a common ground, the filter inductor can be connected to the ground terminal, as shown in Figure 7. Using this structure, the source of the N-FET is the output voltage VO. This makes the circuit for driving the FET simple and reliable, and the VC and VCC voltages can be taken from the same point. However, the forward voltage conversion through the inductor is clamped by the output voltage, so the SYNC synchronization pulse signal must be obtained from another secondary output.

Figure 8 SSPR application with negative voltage output

There are two ways to generate a negative voltage output. One is to simply reverse ground at the output, as shown in Figure 8. The SSPR circuit supports negative voltage output.

Figure 9: Negative voltage output SSPR application with reference to ground

Another method is shown in Figure 9. The reference of the gate drive circuit of SSPR is the power ground. In this structure, the feedback signal needs to be inverted. In
the push-pull or bridge double-terminal topology, only one power switch is needed to control the output voltage. As shown in Figure 10. The output filter inductor can be connected to the output positive terminal or the output ground terminal. The operating frequency is twice the switching frequency of the primary controller.

Figure 10: Double-ended topology SSPR application

For high power supply, single package rectifier application with center lead, the gate drive circuit of SSPR power switch can be realized by isolation transformer, as shown in Figure 11.

Figure 11 SSPR application driven by isolation transformer

Design Example
Below is a design of a dual-output current mode controlled forward converter. The main 5.0V output uses a PWM controller (CS3842A), and the auxiliary 3.3V output uses a CS5101 controller.

Design parameters
Input voltage range 18~36Vdc, main output VO1/IO1: 5.0Vdc/0.2~3.0Adc, auxiliary output VO2/IO2: 3.3Vdc/0.3~2Adc, switching frequency 100kHz, main and auxiliary line linear adjustment rate, load adjustment rate are both <1.0%

The power transformer uses TDK core PC40EER25.5-Z. The 3.3V output and 5V output use the same number of turns. The turns ratio of the power transformer NPY:NSY5:NSY3:NAUX is equal to 20:11:11:8. Duty cycle range: Dmax = 0.586, Dmin = 0.293. The 5.0V output inductor L1 = 100μH, using a T72-26 FeSiAl magnetic ring, 34T, #24AWG. The 3.3V output inductor L2 = 50μh. Use a T80-26 FeSiAl magnetic ring, 42T, #24AWG. Each of the two outputs uses an aluminum electrolytic capacitor, 330μf/15V, ESR = 0.12Ω. Because the converter adopts current mode control, the sampling of the primary peak current is obtained through the current sampling resistor R10. The change of the primary side current slope is affected by the secondary two output inductors. At the lowest input voltage, the duty cycle exceeds 50%, and slope compensation is necessary to avoid loop instability.

SSPR control output calculation
From the above data, we can see that the 3.3V winding voltage at low voltage input is: VSY3=18×(11/20)=9.90V.
Assuming that the forward voltage drop of the Schottky rectifier is 0.75V and the forward voltage drop of the FET is 0.1V at full load, the duty cycle correction is:
DO3LL=(3.3+0.75+0.1)/9.9=0.419
DO3HL=(3.3+0.74+0.1)/19.8=0.209.
The supply voltage VCC is directly taken from the 3.3V winding, which changes with the input voltage, VCC＝9.0V～19V. The reference of Vcc is ground, and the reference point of the gate drive voltage VC is the source level of Q3, VC = 8.0V～18V.
The synchronous voltage threshold of CS5101 is 2.5V. For reliable operation, the voltage on the SYNC pin must be above 2.5V during the pulse.
VSYNC(MIN)=VSY(MIN)×(R14/(R13+R14))=((18×11)/20)×(15K/(5.1K+15K))=7.39V
VSYNC(MAX)=((36×11)/20))×15K/5.1K=14.87V
Since the voltage on the coil is negative during the recovery period, a clamping diode D9 is connected in parallel with R14.
The value of the ramp capacitor is calculated using the minimum on-time (at high voltage input) and the internal current source current. CRAMP=C16=300PF.
The output current can be obtained by the current sampling resistor R19 at the negative end of the output. The voltage divider composed of resistors R16, R17 and R20 is connected to the current amplifier to calculate the overcurrent protection set point.
Design results and waveforms
The circuit electrical performance parameters are shown in Table 1.

It can be seen from the table that the 3.3V output load effect and source effect are both better than 0.3%.
The actual waveforms are shown in Figure 12 and Figure 13.

Figure 12 Primary side waveform

Figure 13 SSPR waveform