DSP Implementation of Power Factor Correction of Switching Power Supply

As the demand for high power factor converters continues to grow, power supplies with a unity power factor are becoming more and more popular. In computers or other devices, the power supply requires good robustness, reliability, and strong anti-interference ability. Digital control provides this guarantee.

Compared with traditional analog controllers, digital controllers have the following advantages: they can implement nonlinear and sophisticated control algorithms, reduce the number of components, improve reliability, are not prone to aging, and have very small control deviations and thermal drifts. But at the same time, digital control also means relatively high costs and certain control bandwidth limitations. In the past, these shortcomings have largely limited the application of digital control in power supplies. Now, due to the emergence of efficient and inexpensive DSPs, digital control is not only increasingly used in AC drives and three-phase conversion, but has also become a feasible solution in the field of DC/DC conversion. This article will discuss the application of DSP in single-phase switching power supply power factor correction.
2 Introduction to traditional analog PFC circuits

Analog PFC circuits have been used for many years, and some commercial IC chips have been launched, such as TI's UC3854.

Figure 1 shows the basic principle of power factor correction. The PFC control circuit is mainly composed of a voltage error amplifier, a current error amplifier, a multiplier and a PWM driver. The control goal is to make the input current closely follow the input voltage change and make the output ripple as small as possible. In order to make the input current follow the input voltage change, the control circuit samples the input voltage and the sampling signal is used as one input of the multiplier; in order to keep the input voltage stable, the output voltage is divided, compared and error amplified as another input of the multiplier, so the output of the multiplier has the shape of the input voltage, and its amplitude is controlled by the output voltage. The output of the multiplier is used as the reference signal of the input current. The input current is sampled, compared with this reference, and input into the PWM comparator after error amplification. The PWM output drive waveform controls the operation of the converter. The result of closed-loop feedback control makes the average value of the input current proportional to the input voltage, thereby achieving a higher power factor.

Figure 1 Power factor correction principle

The output of the PFC converter contains a second harmonic ripple voltage.

|ΔVo(t)|= （1）

This has nothing to do with the converter's topology and control method. If the output voltage ripple is eliminated through the voltage loop, the input current waveform will inevitably be damaged, thereby reducing the power factor.

If the analog components are too discrete, they will introduce undesirable phase effects, and it is difficult to achieve accurate filtering due to factors such as large parameter discreteness, easy aging and thermal drift. Therefore, for 50Hz power frequency input, the bandwidth of the voltage loop is generally only selected in the range of 10-20Hz.

3 Digitally controlled PFC model

As shown in Figure 2, it is the digital model of the Boost circuit PFC. The control principle of this model is consistent with the analog circuit described above. The difference is that two digital proportional integral controllers (PI) Ki and Kv are used to replace the original two error amplifiers. In addition, a notch filter is added to the output of the voltage PI with a filtering frequency of 100Hz. Compared with the analog filter, the digital filter can well reduce the 100Hz harmonic component, while the phase effect introduced is much smaller.

Figure 2 Digitally controlled PFC model

In this way, the bandwidth of the voltage loop can be increased, thereby improving the response speed of the circuit.

As shown in Figure 2, three signals are sampled, namely the output voltage Vo, the input current Is, and the input voltage Vi'. One point worth noting is that we can program to always sample Is at the middle time of the switch closing, so that the average value of Is can be obtained without adding a low-pass filter.

Next, we build the digital models of the PI controller and the notch filter respectively. The simulation expression of the PI control algorithm is

V(t)=Kp （2）

Discretize equation (2) and get

V(n)=Kp[e(n)-e(n-1)]+Ki·e(n)+V(n-1) (3)

Where: Kp is the proportional coefficient; Ki=Kp is the integral coefficient, T is the sampling period, and Ti is the integral time constant.

The setting of PI coefficient is usually determined by experiment, trial and error, or empirical formula. This aspect is generally introduced in books on computer control systems.

The design of the notch filter can refer to formula (4)

(4)

Where: ω is the angular velocity of the filter frequency; Q value is determined according to different requirements.

Discretization can be easily achieved by Matlab's sysd=c2d(sys,Ts) equation. Figure 3 shows the Matlab simulation of the designed filter, where ω=628 and Q=20.

Figure 3 Matlab simulation of digital notch filter

4 DSP Implementation

We use TI's 16-bit chip TMS320LF2407A to implement the control scheme. This chip is specially used for the 2000 series of digital control, adopts Harvard structure CPU and 4-level pipeline operation program control, and runs at a speed of 40MIPS (i.e. 25ns instruction cycle). It has 544 bytes of DARAM, 2k SARAM, 32k FLASH, 2 event management units, 16-channel 10-bit, 500ns conversion time A/D conversion, up to 16-channel PWM output and other on-chip resources.

For the current loop and voltage loop, we adopt the control frequency of 20kHz and 10kHz respectively. Two interrupt programs are used to complete the digital control of PFC. The interrupt program int2 is responsible for the sampling of 3 inputs and the PI control of the current loop, and the other interrupt program int3 is responsible for the PI control and notch filtering of the voltage loop. Figure 4 is the main program control flow chart, and Figure 5 is the sampling cycle chart. The interrupt priority of int2 is higher than that of int3, so if int3 is not completed and the int2 interrupt occurs, int3 will be suspended until the int2 interrupt program ends before continuing to run. Because the voltage loop changes slowly, a delay of one cycle will not affect the control effect. Set the comparison control register, write a new comparison value when T1 underflows, and combine the value of the general timer period register T1PR to generate a new duty cycle PWM wave to control the action of the switch connected to it. From Figure 5, we can also notice that the interrupt program of int2 (including 3 samplings and a PI program) must be completed within half a current sampling cycle, that is, within 25μs. According to the performance indicators of DSP given above, this goal can be fully achieved.

Figure 4 Main program flow chart

Figure 5 Sampling cycle diagram

In addition, in practical applications, the integral separation PI algorithm is used to limit the output value of PI within a certain range to avoid large overshoot of the system and cause system oscillation. A soft start program is also added to gradually increase the value of Vref at the beginning of the program to meet the soft start requirements of the switching power supply.

Because parameters such as Kp, Ki and filter coefficients are all floating-point numbers, and a 16-bit chip is used, the above algorithm needs to be implemented with DSP to solve the problem of conversion between floating-point numbers and fixed-point numbers. Different Qn values ​​can be used to express floating-point numbers of different ranges and precisions, where n represents the number of digits after the decimal point in 16 bits. For example, Q0 can represent integers from -32768 to 32767, while Q15 can express real numbers from -1 to 0.9999695 with a precision of 1/32768 [2]. Different Qn values ​​need to be shifted and converted to the same number of digits before they can be compared and added or subtracted.

5 Experimental Results

After the program is compiled, it is burned into the on-chip flash, and with the addition of a simple peripheral circuit, it can be experimentally verified. We use the topology of the Boost circuit, connected to a resistive load, with an input voltage of 220V and an output voltage of 385V. The input voltage and current waveforms are shown in Figure 6. The input power of the PFC circuit is 545W and the output power is 513W measured by a power meter. The conversion efficiency of the PFC circuit can be calculated to be 94.1%. Under the same test conditions, the power factor of the PFC circuit measured by a power factor meter is 0.983. Figure 7 shows the soft start process.

Figure 6 BOOSTPFC circuit input voltage and current diagram

Figure 7 Soft start waveform

6 Conclusion

This paper discusses the full digital implementation of power factor adjustment for switching power supplies, and the feasibility of the scheme is proved by experiments. At present, there are not many studies on the use of DSP control for switching rectifier devices, mainly because the price of DSP is relatively high compared to dedicated integrated chips, and mature control algorithms are difficult to obtain. However, with the continuous reduction of DSP chip prices and the deepening of control algorithm research, it is believed that the era of digital control of switching rectifier devices will soon come.