Revealing the secret: How to improve the standby efficiency of switching power supplies

As energy efficiency and environmental protection become increasingly important, people have higher and higher expectations for the standby efficiency of switching power supplies . Customers require power supply manufacturers to provide power products that meet green energy standards such as BLUE ANGEL, ENERGY STAR, and ENERGY 2000. The EU's requirements for switching power supplies are: by 2005, the standby power consumption of switching power supplies with rated power of 0.3W~15W, 15W~50W, and 50W~75W must be less than 0.3W, 0.5W, and 0.75W, respectively. However, when most switching power supplies are currently switched from rated load to light load and standby state, the power efficiency drops sharply, and the standby efficiency cannot meet the requirements. This poses new challenges to power supply design engineers .

2. Switching power supply power consumption analysis

To reduce the standby loss of the switching power supply and improve the standby efficiency, we must first analyze the composition of the switching power supply loss. Taking the flyback power supply as an example, its operating loss is mainly manifested as: MOSFET conduction loss

MOSFET parasitics capacitance loss

Switch overlap loss, PWM controller and its startup resistance loss, output rectifier loss, clamp protection circuit loss, feedback circuit loss, etc. The first three losses are proportional to the frequency, that is, proportional to the number of device switches per unit time.

In standby mode, the main circuit current is small, the MOSFET conduction time ton is very small, and the circuit works in DCM mode, so the related conduction loss, secondary rectifier loss, etc. are small. At this time, the loss is mainly composed of parasitic capacitance loss, switch overlap loss and startup resistance loss.

3. Methods to improve standby efficiency

According to the loss analysis, cutting off the startup resistor, reducing the switching frequency, and reducing the number of switches can reduce the standby loss and improve the standby efficiency. The specific methods are: reducing the clock frequency; switching from high-frequency working mode to low-frequency working mode, such as switching from Quasi Resonant mode (QR) to Pulse Width Modulation (PWM), and switching from Pulse Width Modulation to Pulse Frequency Modulation (PFM); controllable pulse mode (Burst Mode).

3.1 Cut off the starting resistance

For a flyback power supply, after startup, the control chip is powered by an auxiliary winding, and the voltage drop across the startup resistor is about 300V. Assuming the startup resistor value is 47kΩ, the power consumption is nearly 2W. To improve the standby efficiency, the resistor channel must be cut off after startup. TOPSWITCH, ICE2DS02G has a dedicated startup circuit inside, which can turn off the resistor after startup. If the controller does not have a dedicated startup circuit, a capacitor can also be connected in series with the startup resistor, and its loss after startup can gradually decrease to zero. The disadvantage is that the power supply cannot restart itself, and the circuit can only be started again after the input voltage is disconnected and the capacitor is discharged. The startup circuit shown in Figure 1 can avoid the above problems, and the power consumption of the circuit is only 0.03W. However, the circuit increases complexity and cost.

Figure 1 UC3842 flyback power supply startup circuit

3.2 Reduce the clock frequency

The clock frequency can be smoothly decreased or dropped suddenly. Smooth decrease means that when the feedback exceeds a certain threshold, the clock frequency is linearly decreased through a specific module. POWER's TOPSwitch-GX and SG's SG6848 chips have such a module built in, which can adjust the frequency according to the load size. Figure 2 shows the relationship between the SG6848 clock frequency and its feedback current .

Figure 2 Relationship between SG6848 feedback current and clock frequency

The sudden drop implementation method is shown in Figure 3: Taking UCC3895 as an example, when the power supply is in a normal load state, Q1 is turned on and its clock cycle is:

That is, the switching frequency is reduced. The switching loss is reduced to

(less than 1) times. L5991 and Infineon's CoolSet F2 series have integrated this function.

3.3 Switching working mode

3.3.1 QR→PWM

IR IS40xx chip improves standby efficiency by switching between QR and PWM. Figure 4 shows a flyback switching power supply composed of IRIS4015. When overloaded, the auxiliary winding voltage is large, the R1 voltage is greater than 0.6V, Q1 is turned on, and the auxiliary quasi-resonant signal reaches the FB pin of IRIS4015 through the delay circuit composed of D1, D2, R3, and C2 . The internal comparator compares the signal and the circuit works in quasi-resonant mode. When the power supply is lightly loaded and in standby mode, the auxiliary winding voltage is small, Q1 is turned off, the resonant signal cannot be transmitted to the FB terminal, and the FB voltage is less than a threshold voltage inside the chip, which cannot trigger the quasi-resonant mode. The circuit works in a lower frequency pulse width modulation control mode.

3.3.2 PWM→PFM

For a switching power supply that works in PWM mode at rated power , the standby efficiency can also be improved by switching to PFM mode, that is, fixing the on-time and adjusting the off-time. The lower the load, the longer the off-time and the lower the operating frequency. Figure 5 is a comparison curve of the efficiency of the Buck converter circuit controlled by NS's LM2618 and the PWM and PFM control methods. As can be seen from the figure, the efficiency of the power supply using PFM mode is significantly greater than that using PWM mode at light load, and the lower the load, the more obvious the PFM efficiency advantage. The standby signal is added to its PW/ pin. Under rated load conditions, the pin is high and the circuit works in PWM mode. When the load is below a certain threshold, the pin is pulled low and the circuit works in PFM mode. Switching between PWM and PFM improves the power efficiency in light load and standby states.

By reducing the clock frequency and switching the working mode to reduce the standby operating frequency and improve the standby efficiency, the controller can be kept running all the time, and the output can be properly regulated in the entire load range. Even if the load surges from zero to full load, it can respond quickly, and vice versa. The output voltage drop and overshoot values ​​are kept within the allowable range.

3.4 Controllable Burst Mode

Controllable pulse mode, also known as skip cycle control mode, means that when in light load or standby conditions, a signal with a period larger than the PWM controller clock period controls a certain part of the circuit, making the PWM output pulse periodically effective or ineffective, as shown in Figure 6. In this way, the efficiency of light load and standby can be improved by reducing the number of switches and increasing the duty cycle at a constant frequency. This signal can be added to the feedback channel, PWM signal output channel, PWM chip enable pin (such as LM2618, L6565) or chip internal module (such as NCP1200, FSD200, L6565 and TinySwitch series chips).

The internal skip cycle module structure of NCP1200 is shown in Figure 7. When the voltage of the feedback detection pin FB is lower than 1.2V (this value is programmable), the skip cycle comparator controls the Q trigger to turn off the output for several clock cycles, that is, skip several cycles. The lighter the load, the more cycles are skipped. To avoid audio noise, the skip cycle mode is only effective when the peak current drops to a certain set value.

Figure 7 NCP1200 cycle skip module structure

The FSD200 realizes controllable pulse mode by controlling the internal driver.

The feedback voltage of the pin is compared with the 0.6V/0.5V hysteresis comparator, and the gate drive output is controlled by the comparison result. Its structure can be seen in Figure 8. Based on this principle, we can use discrete components to implement the Burst Mode function of ordinary chips , that is, detect the secondary voltage to determine whether the power supply is in standby state, and control the chip output through the hysteresis comparator . The circuit is shown in Figure 9.

Controlling the feedback channel is one of the methods to achieve the controllable pulse mode of a general PWM controller. The circuit can be seen in Figure 10.

yes

Feedback signal, when the Burst Signal is low, Q1 is turned off.

The circuit works normally. When the Burst Signal is low, Q1 is turned on and R1 is short-circuited.

Flow through Q1

Pulled up to

-0.6V, feedback signal

Cannot be reflected in

Therefore, the controller outputs a low level.

In addition, for PWM controllers with an enable pin, such as L6565, the Burst Mode can also be implemented by using a controllable pulse signal to control the enable pin to enable or disable the control chip. The above-mentioned Burst Signal can be generated by the hysteresis comparator shown in Figure 1.

Figure 10 Burst Mode of Control Feedback Channel

4 Problems

The frequency reduction and Burst Mode methods introduced above improve the standby efficiency, but also bring some problems. First, the frequency reduction leads to an increase in output voltage ripple. Second, if the frequency drops below 20kHz, there may be audio noise. During the OFF period of Burst Mode, if the load surges, the output voltage will be greatly reduced. If the output capacitor is not large enough, the voltage may even drop to zero. If the output capacitor is increased to reduce the output voltage ripple, it will lead to increased costs and affect the dynamic performance of the system. Therefore, comprehensive consideration must be given.