Current Control Technique and Slope Compensation

4. Ringing inductance Current

① The inductor current produces a ringing response to transient changes in the power supply or load;

② The control loop gain reaches its maximum near the switching frequency, resulting in an unstable trend.

This ringing inductor current can be suppressed by slope compensation. For example, when the compensation slope is the slope of the falling edge of the inductor current (ie m=-m2), the ringing current is completely suppressed within one cycle.

Figure 9 Relationship curve between equivalent inductor current, current error and period T

Slope compensation design steps:

Figure 10 shows a slope compensation circuit . R1 and R2 form a voltage divider network from the output of the crystal oscillator to the current limiting pin (pin 1), superimposing the slope compensation signal to the primary current waveform. The ratio of the R1 and R2 values ​​determines the amount of slope compensation added. Capacitor C1 is an AC coupling capacitor, which couples the AC component of the crystal oscillator to R2 and removes the DC bias part. C2 and R1 form a filter circuit to filter out the leading edge peak in the primary Ip to avoid false operation. ? VOSC is the peak-to-peak value of the crystal sawtooth wave. Removing the capacitor gives the simplified circuit of Figure 11.

Figure 10 Slope compensation circuit

Figure 11 Simplified slope compensation circuit

4. Application of current control technology and slope compensation

1. Average current method Boost circuit Design example

Design a 1200W power factor correction circuit, using the Boost circuit topology, average current method control circuit, and UC3854BN control chip . The circuit parameters are as follows:

Input voltage : Vin=220V±25%(165V～275V);

DC output voltage: VO=410V;

Switching frequency: fs=80kHz;

Power factor: PF>0.993;

Efficiency:?>0.95;

Inductance: L = 600μＨ;

Detection transformer ratio: 1:100;

Detection Resistance : 15O.

① In order to ensure stable operation of the current loop design, current loop phase compensation must be performed.

After the current loop is compensated, it provides a stable gain near the switching frequency. The zero response at low frequency provides high gain to complete the average current control work. The gain of the error amplifier near the switching frequency should match the falling edge of the inductor current. The switching frequency of this design is 80KHz, and the unity gain crossover frequency should be 14KHz (1/6 switching frequency), but the main work of this current loop is to track the line current, so the bandwidth of 10KHz is a suitable value. The zero point of the current loop must be set at the crossover frequency or below the crossover frequency. If it is set at the crossover frequency, the phase margin is 45°, and the phase margin is larger below the crossover frequency. The system with a phase margin of 45° works stably, has low overshoot and small interference, so the zero point is set slightly below the crossover frequency (fs is 10KHz). When the pole is higher than 1/2 of the switching frequency, the pole will not affect the frequency response of the control loop. In order to reduce the sensitivity to noise, the pole is usually set near the switching frequency. This design sets the pole at the switching frequency (fp is 80kHz). The process of designing the current loop is to first calculate the gain of the power part at the zero point, and the power part gain multiplied by the current amplifier gain is the gain of the entire current loop. When the gain of the entire current loop is 1, the crossover frequency (i.e., zero point) of the current amplifier is calculated, and the gain of the current loop at the crossover frequency is the inverse of the power part gain. From this, the gain of the current loop is calculated, and the resistance of the compensation network is calculated from the gain. The zero point capacitance of the compensation network is calculated from the resistance and the zero point frequency , and then the pole capacitance of the compensation network is calculated from the pole frequency. The specific calculation process is: the falling edge of the inductor current = (Vo-Vin)/L; the worst case (Vin=0), the falling edge of the inductor current =Vo/L; the crystal slope =Vs/Ts=Vsfs.

Because the output of the current amplifier cannot be greater than the output of the crystal oscillator, that is, the slope of the inductor current cannot be greater than the slope of the crystal oscillator, so when the gain of the current amplifier is maximum, the two input signals of the PWM comparator are equal, at this time:

s and the gain of the power part at the zero point is:

Because the entire current loop has unity gain at the crossover frequency, the current loop gain is 1. The current loop gain and crossover frequency are:

ca G ——Current Amplifier gain

id G ——Gain of the power section

se V ——Peak-to-peak value of crystal oscillator

rs V ——Detection Resistor Voltage

ca V ——current amplifier output voltage

sense R ——Detection resistor

i R ——From the current detector to the inverting input of the current amplifier

The gain diagram of the current loop (Figure 13) and the circuit diagram of the current error amplifier (Figure 14) are shown below.

Figure 13 Current Ring Bode plot

Figure 14 Current loop error amplifier

② Voltage loop design In order to ensure stable operation, voltage loop compensation must be performed.

Compared with stability, the voltage loop of the power factor correction circuit needs to keep the input line current distortion small. The bandwidth of the voltage loop must be designed to be low enough to attenuate the second harmonic of the power frequency on the output capacitor ; the voltage error amplifier must also have enough phase margin to track the input current in phase to improve the power factor. The low-frequency mode of the output part of the Boost circuit is a first-order circuit of the current source driving the capacitor. The power part and the current feedback loop constitute the current source, and the output capacitor constitutes the capacitor. This mode has a gain characteristic of -20dB/decade. If the voltage feedback loop is closed near this, it will have constant gain and be stable, but it has poor performance in suppressing the distortion caused by the second harmonic. The amplifier needs a pole to reduce the ripple voltage gain and make the phase shift 90°, thereby finding the unity gain crossover frequency and pole position. The design of the voltage loop is related to the THD to be achieved. The 1.5% second harmonic generated at the output of the voltage error amplifier will generate 0.75% third harmonic at the input of the circuit.

Because the design requires THD to be no more than 3%, the output ripple ratio allowed to be allocated to the voltage error amplifier is 1.5%. In order to provide sufficient phase margin, the pole is set at the crossover frequency, and the entire loop gain will be at a phase margin of 45°. The design of the voltage loop starts with calculating the 2nd harmonic voltage allowed on the output capacitor , then calculating the 2nd harmonic output allowed by the voltage amplifier, and then calculating the 2nd harmonic gain value of the voltage amplifier, from which the compensation capacitor of the voltage loop can be calculated. The gain of the power part and the gain of the voltage loop constitute the gain of the entire voltage loop. When the gain of the entire voltage loop is 1, the crossover frequency is calculated. Then the resistance of the compensation network is calculated from the crossover frequency . The calculation method is as follows:

When q=24, k<0.105 will ensure soft switching . When Troff<(1-Dmax)Ts=0.1Ts, Troff is minimum. When q=24, k<0.09. Taking all factors into consideration, k=0.09 should be used;

③ Lr=6.5μＨ, its value is obtained according to k;

④ Ls=30μH, the most direct way to determine the Ls value is to require that the Vr operating range satisfies V/10

⑤ Cs=2μF, CS can be regarded as a relatively constant value during the entire switching cycle. This ensures that the resonant period of Ls and Cs is several times the switching period.
2. Peak current control chip UC3846 performs slope compensation circuit design example

The main circuit topology adopts a dual-tube forward-pulse circuit

UC3846 slope compensation selection circuit According to the peak current control circuit diagram, there are two ways to add slope compensation. One is to add the slope compensation signal to the current detection signal. The former is simple to implement, but due to the addition of the slope compensation signal, it is possible to produce errors when implementing the current limiting function.
The second method must meet two conditions when implementing: ① Near the switching frequency, the gain of the voltage amplifier must be a fixed constant R1/R2; ② When the emitter slope is compensated, both the current amplifier and the voltage amplifier must be taken into account. Parameter selection A single-ended forward circuit is used to design a 1000W communication power supply , with UC3846 as the control chip, AC input 165~275V; output 50V, 20A; operating frequency 80k Hz; turns ratio 8/1 (Np/Ns), detection resistor Rsense=0.4O; output inductor L=40uH; crystal capacitor CT=1nF; dead time 0.145us.