National Semiconductor Case Study: Solving the Design Problem of Current Mode Control in SMPS Applications

The standard control method used in early switch mode power supply (SMPS) designs is called " voltage mode" operation. A ramp generator drives one input of a voltage comparator, and the error signal from the error amplifier/loop filter drives the other input, see Figure 1. The result is a PWM pulse based solely on the voltage error signal. Circuits in this mode of operation have the following two limitations: first, there is no current limiting function to protect circuit components, and second, the response to transient changes in input and output is slow.

Figure 1 Voltage mode control

Current Mode Control

As SMPS designs mature, a safer system called "current mode" control is gradually coming into the designer's sight. This system replaces the ramp generator with a current feedback signal driven by the inductor current. The system's inductor peak current obtained in this way is directly controlled by the error signal, thus eliminating circuit failures that may be caused by overcurrent conditions, as shown in Figure 2. Since the current mode controls the inductor current, it can effectively eliminate the "poles" and delays caused by the inductor in the control loop, thereby improving the system's transient response speed.

Figure 2 Current mode control

Importance of Slope Compensation

A significant problem with most analog current mode PWM controllers is that they can only measure peak current. Since the output capacitor integrates the average current to produce the desired output voltage, the ability to measure the average current is actually needed. Usually, the average current can be approximated as half of the peak current. For duty cycles less than 50%, there is enough time for the inductor current to decay to zero before the next PWM cycle starts. As long as the inductor current reaches zero at the end of the PWM cycle, the average current is equal to half of the inductor peak current, see Figure 3.

Figure 3 When the duty cycle is less than 50%, the average current is approximately half of the peak current

This design is usually feasible, but some problems will appear when the duty cycle is greater than 50%. The main reason is that the average current is no longer approximately half of the peak current, see Figure 4.

Figure 4 When the duty cycle is greater than 50%, the average current is greater than half of the peak current

As the PWM duty cycle continues to increase above 50%, the average current will become increasingly larger than estimated by measuring the peak current. The resulting output voltage will be higher than expected and will continue to rise until the slower voltage control loop readjusts the current set point. The output voltage will drop below the expected voltage and the process will repeat (called sub-cycle oscillation).

To solve the instability problem of current mode, a technique called “slope compensation” was developed for analog current mode controllers. By adding a falling edge sawtooth voltage to the current threshold generated by the voltage error amplifier, as shown in Figure 5, a new current threshold is generated for the current limit comparator, allowing it to more closely track the average inductor current.

Figure 5 Slope compensation

Design Issues in Digital Current Mode Control

Many of the limitations of analog current-mode PWM controllers are overcome by using digital current-mode control. Digital current-mode control in an SMPS is valuable because it provides many features such as transistor peak current protection, elimination of magnetic field “ratcheting” in magnetic components, input voltage variation rejection, and simple control loop compensation. Implementing current-mode control provides another benefit, which is that the maximum value of the inductor current is controlled using the error voltage, making the inductor a voltage-controlled current source. As a current source, the inductor no longer creates a pole in the frequency response of the loop. This changes the loop from an unconditionally unstable circuit to a conditionally stable circuit, which makes loop filter design much simpler. If current mode is such a superior system, why do digital SMPS designers still use voltage-mode control?

Many DSCs do not have analog comparators and an ADC that can measure the inductor current at the appropriate point in the PWM cycle. Without some way to accurately measure the current at the desired point in time, the DSC must continually measure the inductor current with the ADC during the PWM cycle to capture the "moment" when the inductor current reaches the desired value. To achieve 12-bit resolution, up to 2048 ADC current conversions need to be performed per PWM pulse. The required ADC sampling rate is 1 billion times per second. In addition, sufficient processing power is required to collect these 1 billion conversions, compare each conversion result to the error signal, and turn off the PWM output when the desired current is reached. Conservatively speaking, this means a processor capable of executing 1 billion instructions per second (BIPS). Obviously, this is not a low-cost design solution to this problem.

DSC simplifies the design of SMPS current mode control

So how do designers implement current mode control in digital SMPS designs? The answer is to use the latest digital signal controllers (DSCs) with peripherals that support SMPS designs.

When implementing an SMPS design with a DSC, there are many possible methods for implementing current-mode control. For example, Microchip's dsPIC30F202X DSC has the following features: a high-resolution digital PWM generator, an ADC that asynchronously samples and converts signals at a sampling rate of two million times per second, a high-speed analog comparator with an associated 10-bit reference digital-to-analog converter (DAC), and a 30MIPS high-performance controller with DSP processing capabilities.

On-chip DACs provide programmable thresholds for the analog comparators, and software can update these reference DAC values ​​at any time to set the peak current limit.

The key to the digital current-mode approach is to use a DSC with a specific on-chip PWM peripheral that operates in the same manner as a discrete current-mode PWM generator, see Figure 6.

Figure 6. Counter-based PWM with auto-shutdown function

From the block diagram in Figure 2, we can see that two mixed-signal components (a voltage comparator and a DAC) have been added to the normal timer-based PWM peripheral. The voltage comparator provides a shutdown signal to the PWM module, which, together with the output of the duty cycle counter, gates the PWM signal. When the duty cycle counter reaches 0, the output of the comparator can drive the PWM output to 0.

The DAC takes input from the DSC and generates the reference signal for the comparator. When the system is integrated into a digital SMPS, the counter in the PWM module generates PWM pulses, the DAC generates a voltage that is sent to the inverting input of the comparator (this voltage represents the desired current in the inductor), and the feedback current is sent to the non-inverting input of the comparator.

As the current in the inductor builds, the duty cycle counter will continue to count upward. If the inductor current reaches the desired value first, the comparator will terminate the pulse and the inductor will begin to discharge into the output capacitor . If the PWM counter reaches the specified duty cycle value first, the comparator will terminate the PWM pulse. This approach achieves the best of both worlds - you get a fast current mode feedback that does not require a high MIPS processor, but you also have the ability to set a maximum duty cycle to limit current.

Implementing digital current mode design

How do we make this system work? We first determine the PWM frequency and maximum duty cycle required for the SMPS design. These parameters are used to configure the counter portion of the PWM. Next, the reference DAC output is adjusted to the maximum range of the desired current feedback signal. This provides the highest resolution when controlling the PWM duty cycle. Finally, the proportional-integrator-differentiator (PID) software code is designed, which receives the voltage feedback from the ADC, compares it to the internal digital reference voltage, filters it appropriately to aid stability, and then outputs the desired current setting to the DAC that generates the comparator reference voltage, see Figure 7.

Figure 7 Digital current mode control

How to deal with the current mode stability problem when the duty cycle is greater than 50%? The PID software sets the desired current value, so the DAC value can be easily adjusted. Since the digital control operation is all done by software, it is easier to do slope compensation digitally than in analog. The analog solution requires a ramp generator synchronized with the PWM pulse and a summing node (the ramp voltage is added to the current feedback).

This approach designs a simple current-mode SMPS system that uses a cost-effective 30 MIPS DSC to do the work that would be difficult for a 1-2 BIPS processor to do. Assuming that the processor only needs to calculate a new desired current value before the next pulse begins, the processor should have enough free time to complete other tasks such as communication, system monitoring, and decision-making functions (including soft-start/power-up sequences and handling fault detection and recovery).

Digital Current Mode Control Technology

The DSC contains an ADC that can accurately sample the specific current during the PWM cycle, which allows current mode control without the use of analog comparators. The digital current mode control loop is based on the fact that the PWM on-time required to achieve the desired inductor current value can be calculated. The voltage across the inductor can be measured, and when the inductance is known, the initial current in the inductor can also be measured.

Given: V=Ldi/dt
I(t)=I(to)+1/L*∫V(t)dt

Arranged as: (L/V)*(I(t)-I(to))=dt

Use the formula: PWM on-time = (L/V)*2*(Idesired-Istart)

For most applications, the input voltage cannot change quickly due to the large input filter capacitors . Therefore, the time-consuming division operation (L/V) does not need to be calculated every time the control algorithm is executed. The calculation result can be shared across many PWM cycles to reduce the computational effort. By treating the L/V term as a constant, the calculation of the rest of the duty cycle is easy. Not using the analog comparator as a shutdown controller for the PWM signal allows it to be used to detect unexpected large transient changes in load current or output overvoltage conditions.

Feed-forward technology

One of the advantages of current mode control is the improved response to variable input voltages. With digital control in SMPS systems, it is easy to provide feed-forward compensation for variable input voltages. The transfer equations used in most SMPS topologies to describe the relationship between output voltage and input voltage, duty cycle, and transformer turns ratio are relatively simple. Voltage feed-forward can be added at the current set point or in parallel with the current control loop . For example , the transfer equation for a buck converter is:

Vout=Vin*duty cycle/period

Typically, the desired results of all control calculations are used to generate the values ​​to be loaded into the PWM duty cycle registers.

Duty cycle = Vout*(period/Vin)

The time taken to calculate the feed-forward compensation for the input voltage is the time required to perform the division operation. The feed-forward compensation technique is inherently very stable and provides faster transient response.

in conclusion

This article discusses various methods of implementing current mode control in SMPS applications (with or without analog comparators). A DAC with the right peripherals offers a variety of options when implementing an SMPS. An important step in the transition from analog to digital SMPS control is to realize that the desired functionality of current mode control is fully achievable in a DSC using a variety of techniques.