Design of driving system for full-frame CCD image sensor based on CPLD

0 Introduction

Charge coupled devices ( CCD ) are new semiconductor integrated optoelectronic devices developed in the early 1970s . As a new type of MOS device, compared with ordinary MOS devices, it has the advantages of higher integration, lower power consumption, simpler design, and fewer manufacturing processes. With the development of aerospace technology, CCD cameras with superior performance have been increasingly used in the fields of high-attitude and high-accuracy measurement of spacecraft , space remote sensing, and earth observation.

Here, CCD is applied to digital aerial survey cameras. Digital aerial survey cameras are based on the basic principle of digital cameras, storing and transferring images in the form of digital information and communicating with the ground . CCD image sensor is the eye of the camera, which plays a very critical role in the performance of the camera. Therefore, the CCD drive circuit that realizes the electronic scanning function is the key to the design of the digital aerial survey camera system.

DALSA's FTF4052M 22M Full-Frame CCD is a full-frame CCD image sensor. After analyzing the working process of the device and the requirements for the driving signal, the CCD driving circuit is integrated on a chip based on programmable logic device ( CPLD ) technology, realizing the driving circuit of the CCD image sensor, and combining with Ahera's EPM7160SLC84-10 to complete the hardware circuit design.

1 Principle of full-frame CCD drive timing generator

1.1 Introduction to FTF4052M chip

FTF4052M is a 22-megapixel (4 008 pixels × 5 334 pix-e1) ultra-large resolution full-frame CCD image sensor. Its internal structure is shown in Figure 1.

Its main features are as follows:

(1) 36 mm × 48 mm photosensitive surface;

(2) Excellent anti-halation performance;

(3) 22 megapixels (8H x 5 344V);

(4) Vertical subsampling can be achieved;

(5) High linear dynamic range (>72 dB);

(6) Data transmission rate up to 27 MHz;

(7) Single, dual and quadruple outputs can be realized simultaneously.

The chip is structurally divided into three parts. The largest area in the middle is the photosensitive area, i.e. the light integration area; the upper and lower parts are two output registers. The charge generated by light integration is horizontally transferred to the output amplifiers at the four corners. The output amplifiers amplify the voltage signal formed by the photogenerated charge and transfer it out of the CCD.

C1, C2, and C3 are the clock signals of the horizontal pixel transfer register . A1, A2, A3, and A4 are the vertical line drive clock signals. TG is the barrier between the photosensitive area and the output register; OG is the output gate; sG is the last gate before the output gate; and RG is the output amplifier. The biggest feature of this chip is that it divides the image generated by the photosensitive area into four symmetrical quadrants: W, X, Y, and Z. The charge in each quadrant can be transferred in different directions and output simultaneously through four output terminals, which effectively improves the frame rate. The frame rate of single-end output is 1 frame/s, while the frame rate of four-end simultaneous output can reach 3.6 frames/s.

1.2 Frame transfer timing analysis

The entire frame transfer sequence of CCD is shown in Figure 2, which is mainly divided into three stages, and these three stages are carried out periodically. Here, the idle mode stage is defined as the first stage. In the idle mode of the CCD chip, all A clock signals remain at a low level. After the idle mode, the CCD chip begins to enter the second stage, namely the light integration stage.

As shown in Figure 2, SSC is the internal reference clock signal of the system, which is used to calibrate the timing of the entire CCD. VA high is the high-low level conversion signal that controls the four groups of A clocks; the phase and frequency of the TG signal are exactly the same as A1. Since the CCD chip FTF4052M serves as a full-frame CCD chip, the photosensitive surface occupies most of the CCD area. In order to obtain a 100% pollution point image, a mechanical shutter must be added. Its opening is completed by the Trig-in signal. When the rising edge of the Trig-in signal arrives, the shutter is triggered to open, and the CCD is ready for light integration. After the rising edge of the Trig-in signal, when the first rising edge of the reference clock signal SSC arrives, a signal CR with a pulse width of 190.6 ps is generated to initialize the CCD. When the CR pulse reaches the falling edge, the shutter is completely opened, and the CCD officially enters the light integration stage. A1 continues to maintain a low level; A2, A3, and A4 rise to a high level. Because each pixel in the CCD chip can be regarded as "covered" by four gates (each gate is connected to a phase clock signal), and the pixels must be separated, and the pixels can be isolated by channels in the horizontal direction. In order to isolate the pixels from each other in the vertical direction, the gate voltage of one of the four gates must be zero. In this system application, A1 is kept at a low level to play the role of pixel isolation. However, the photogenerated charge accumulates under the A2, A3, and A4 gates that are kept at a high level to form a signal charge packet.

After the light integration is completed, it enters the third stage, namely the frame transfer stage. The frame transfer can be regarded as the alternation of vertical line transfer and horizontal pixel transfer. The conversion between them is achieved by the high and low conversion of the SSC level.

The arrival of the rising edge of SSC marks the end of a horizontal pixel transfer and the beginning of a vertical line transfer. The vertical line transfer of CCD pixels is completed by A1, A2, A3, A4 and pixel transfer gate TG clocks, all of which have a frequency of 50 kHz, and the four-phase A clock signal must meet the strict overlapping principle. When SSC maintains a high level, as shown in Figure 3, the charge packets generated in the photosensitive area are transferred up and down to the output register line by line under the drive of the four-phase A clock signal.

When the falling edge of SSC arrives, it marks the end of a vertical line transfer and the beginning of a horizontal pixel transfer. The transfer of CCD pixels in the horizontal direction is completed by clocks such as C1, C2, and C3, and the signal frequency is 25 MHz. The transfer principle is the same as the vertical line transfer principle, and the three-phase C clock signal must also strictly meet the three-phase overlap principle. As shown in Figure 4, the output register transfers the pixels of this row to the output amplifier one by one under the drive of the three-phase C clock signal.

RG (Reset Gate) is a signal that resets the floating diffusion capacitor (FD) of the output amplifier through the reset tube, where FD can convert the received charge packet into a voltage signal. After resetting, FD can receive the next charge packet. SG (Summing Gate) is the last gate before the output gate OG. The phases of the SG signal and the RG signal are the same as the phase of the C3 signal. After a row of charge packets is converted and amplified by the output amplifier, it is output from the CCD in the form of a voltage signal. Next, the vertical row transfer and horizontal pixel transfer output of the next row are performed until all 5,356 rows of charge packets on the photosensitive surface are output. It can be seen that the entire frame of the image is output from the output amplifier of the CCD chip under the alternating drive of the A clock signal and the C clock signal to complete the frame transfer.

2 Drive system design

With the rapid development and widespread use of large-scale programmable devices, the traditional building block circuit system composed of TTL standard circuits has been gradually eliminated. At present, there are generally two popular CCD drive circuit design schemes: one is to use FPGA or CPLD to generate CCD timing drive signals, and use analog circuits ( power amplifier transistors and potentiometers) to realize the DC level drive signal of CCD; the other is to use a dedicated CCD driver chip to drive CCD. The former requires developers to be familiar with hardware description language, and is flexible to implement, highly integrated, and convenient for function upgrades and expansions; the latter only needs to set registers, and programming is relatively simple, but the scalability is slightly poor. Here, Altera's EPM7160SIC 84-10 programmable logic device (CPLD) is used , and Altera's QuartusⅡ integrated development environment is used, and the CPLD is burned and programmed online through a download line connected to a microcomputer. The top-level design uses schematic input to design each functional module, and then uses the hardware description language (VHDL) to program each functional module. This top-down development method realizes the design of high-level complex logic, thereby realizing the softwareization of hardware design.

Through the understanding of the CCD chip, the top-level design is divided into three functional modules, namely, the frequency multiplication module (module 1), the light integration time control and shutter control module (module 2), and the frame transfer module (module 3). The relationship between the functional modules is shown in Figure 5. Module 1 is the frequency multiplication module. By calling this module, the frequency pulse signal required for frame transfer can be generated. Since the CPLD chip generally does not have a PLL module, the delay plus XOR method can be used to achieve frequency multiplication. However, the newer CPLD, such as Lattice's Mac hXo series devices, can directly call PLL, which will not be repeated here. Module 2 is the light integration time and shutter control. The CR pulse signal is generated through the photo command to initialize the CCD and generate an enable signal ENA that remains high during the light integration period. ENA is sent to module 1 and module 3 respectively. The CR signal and ENA can be realized by delaying the key signal Trig-in, which is also relatively simple. The most critical part of this design is the frame transfer module. Its principle is mainly to use three counters to nest each other to generate the required drive signal. Its simple process is shown in Figure 6.

First, the modulo-6 counter sell, the modulo-4764 counter sel2 and the modulo-6 counter sel3 are generated by the CLK clock. Due to the interaction between sell and sel2, when ENA=1 and sel2≥683 (as shown in Figure 3), the corresponding signal values ​​of C1, C2, and C3 can be generated, otherwise all are assigned to 0. A1, A2, A3, and A4 use the main clock signal as the clock after frequency division under the joint action of SEL2 and SEL3. After meeting the conditions listed in Figure 6, the values ​​of A1 to A4 can be given according to the change of SEL2 value.

With this modular design, the light integration time, line transfer frequency and image transfer frequency, line transfer number and pixel transfer number per line can all be adjusted. The program has good portability, can be adapted to different needs, and is also easy to debug.

3 Experimental results analysis

The timing diagram after system simulation of the program is shown in Figure 7. It can be seen that the timing meets the datasheet requirements of the CCD chip. The compiled program is downloaded to the CPLD, and the required drive signal can be obtained through the oscilloscope, as shown in Figure 8.

In the experiment, it was found that although each driving signal in the software simulation can strictly meet the timing relationship required by CcD4052M, the driving signal actually output to the CCD signal still has different degrees of delay. This is mainly caused by two reasons. First, because the behavioral level simulation function in the integrated development environment was used in the early stage of the design, the simulation process did not include delay information, and was only used to verify the correctness of the code behavior, which could be independent of the device, so the output of the CPLD would be different from the simulation result; secondly, after the CCD driving signal is generated by the CPLD, it needs to pass through the subsequent analog driving circuit. Due to the characteristics and differences of the electronic device itself, the driving signal reaching the CCD pin has different delays. Among them, the first error can be solved by performing timing level simulation in the integrated development environment. This simulation adds delay information to each underlying device of the design, and can simulate the behavior that is closer to the actual circuit. The second error is caused by the electronic device itself, and there are individual differences, so it is impossible to perform accurate calculations. The solution is to add a delay chip to the circuit design, set the delay of different delay chips through actual measurement, and correct the errors between the driving signals.

4 Conclusion

The CCD drive system is designed with CPLD chip, which has the characteristics of good performance, low power consumption and small size. The development results of the drive circuit show that the use of CPLD dedicated integrated chip for system design has its own advantages, which can simplify the design, and is easy to debug and has strong scalability.