Usually, FPGA engineers have a headache when compiling large projects because the compilation time is very long, often taking several hours. If it is in the debugging stage, it takes several hours to modify an error each time, which is very inefficient. There are two reasons for the long compilation time: 1. The design has a large resource utilization, and the synthesis, translation, and map require a long time; 2. The design timing is tight, and repeated P&R is required to achieve the best timing state.

If you do not want to modify the project code and want to shorten the compilation time, you can use incremental compilation technology. The basic principle is to recompile only the modified part of the design based on the result of the previous compilation, and the other parts use the result of the previous compilation, which can shorten the overall compilation time. Xilinx has two types of incremental compilation technologies: SmartGuide and Partition.

SmartGuide : This is a global optimization option in ISE. When this option is enabled, the compiler will compare the implementation results of the previous compilation during implementation. The unchanged parts will use the previous results. However, if the timing is tight, the corresponding unchanged parts will be re-implemented according to the situation to meet the timing requirements. SmartGuide can mainly shorten the time of MAP and PAR.

The specific usage of SmartGuide is as follows:

1. Right-click the top module, and then click the SmartGuide option.

Figure 1

2. Select the previous compilation information, where the NCD file contains the physical mapping information of the current design.

Figure 2

3. Click OK to enable SmartGuide.

Partition : For partition-based designs, if the HDL code, timing, physical constraints, and implementation options of a partition are not modified, the implementation tool will use a "copy and paste" operation to retain the information of this partition, thereby shortening the implementation time. After the partition is set, the synthesis and implementation time can be shortened.

Since ISE12.1, ISE software no longer supports the partition option, but the partition function is supported in PlanAhead software (ISE is about to exit the Xilinx software stage. It is said that there will be a Rodin software in the future, and the interface is similar to the current PlanAhead). As shown in Figure 3, right-click the module to be partitioned in the Netlist window, and then select Set Partition.

Figure 3

References :

XAPP918: Incremental Design Reuse with Partitions

Note: In a recent project, in order to shorten the compilation time, I enabled the SmartGuide option, but I found that the timing was always very poor. I remember that the timing score was always 0 before. Then I used various optimizations: adding bufg, adding register beats to the critical path, etc., but the timing could not reach 0. When I was about to despair, I suddenly found that I had enabled the SmartGuide option before. I disabled it and tried it. As a result, the version ran out with a timing of 0. I was both happy and frustrated at the time. Through this experience, I learned some lessons. Although using incremental compilation technology in the debug stage can speed up efficiency, the premise is that your code function and timing must meet the conditions before you can use incremental compilation to continue debugging.