Design and implementation of bit error rate tester based on FPGA

1. Overview
　　In the design and implementation process of communication systems, it is necessary to test the bit error performance of the system. Most of the common bit error rate testers are dedicated to testing various standard high-speed channels, which are not convenient for testing a large number of dedicated channels in practical applications. They are also expensive and complicated to build a test platform. With the rapid development of large-scale integrated circuits, FPGA can achieve more and more complex design functions while maintaining its characteristics of high integration, small size, low power consumption and high cost performance, and is increasingly used in the design and implementation of communication equipment. .

　　This article proposes a solution for a bit error rate tester based on FPGA. It uses an FPGA of Altera's Cyclone series (EP1C6-144T) and related peripheral circuits to implement the bit error test function. The main control computer can use the built-in FPGA The asynchronous serial interface (UART) configures the error tester and reads the error information, and the computer completes the error analysis. At the same time, the solution also provides a simple data display, allowing for qualitative analysis of the communication system's performance without a computer.

2. System composition and work flow
　　According to the completed functions, the entire system can be divided into six parts: test code generation unit, error test unit, interface unit, display unit and clock generation unit, as well as control test software running on the main control computer. The specific block diagram is shown in Figure 1.

　　　　　　Figure 1 Block diagram of the bit error tester.
　　The structure of the closed-loop test platform using the bit error rate tester for bit error rate testing is shown in Figure 2. Comparing Figure 1 and Figure 2, the workflow of the system is described as follows.

　Figure 2 Communication system error test block diagram

　　According to the data rate of the communication system to be tested, the computer configures the clock generation unit through UART to obtain the working clock and parameters of each enabled counter, so that the system works according to the predetermined clock; the test code generation unit is configured according to the settings A good clock will send the test code to the sending device of the system under test; after the sent signal passes through the channel emulator, it will be received and judged by the receiving unit of the system under test, and then the received data and the recovered data clock will be sent to the bit error tester; After the error test unit in the error tester completes the synchronization of the input data and the local data, it compares the input data with the local data and counts the number of errors. Every time the data comparison of two test code cycles is completed, the error information is It is sent to the computer through UART for error statistics. At the same time, the error number is sent to the display unit. After processing, it drives four external seven-segment digital tubes to display the bit error rate within this test code cycle.

3. Key technologies and their implementation
3.1 Generation of test codes
　　This design uses m-sequences as test codes. The m-sequence generator follows CCITT recommendations to generate m-sequences for bit error testing of low-speed data transmission equipment. Its characteristic polynomial is x9+x4 +1, period is 512. Using the pseudo-random characteristics of the m-sequence, the communication performance of the system can be well tested under different input combinations. At the same time, the extremely strong autocorrelation of the m-sequence makes it easy for the tester to synchronize the input data with the local test code for easy testing. Error count.

3.2 Implementation of the error code test unit
　　The error code test unit is the core unit of the entire system, and its functional block diagram is shown in Figure 3. The function of the sequence synchronization tracking unit is to use the autocorrelation characteristics of the m sequence to synchronize the input data with the local m sequence and pass the synchronization information to the symbol comparison unit.

　　We use the autocorrelation of the test sequence-m sequence to achieve synchronization between the received sequence and the local sequence. There are many methods for capturing m-sequences, the correlator method and the loop accumulation method are commonly used. The advantage of the correlator method is that the capture speed is fast, and the capture time usually does not exceed the period of two m sequences. However, the biggest problem of the correlator is that it requires too many logical resources. In contrast, the loop accumulation method requires very few logical resources. Although the capture delay is long, it is usually tolerable in a test environment. In addition, we can also take certain measures to further reduce the capture delay. The working principle of the cyclic accumulator is as follows. After the system is reset, the m sequence generator generates the m sequence according to the preset parameters and stores it in the m sequence buffer. After the symbol synchronization, under the control of the address generator, the m sequence is removed from the buffer. It is read out from the area, and the same input sequence is bitwise ORed and then arithmetic added. The added sum is buffered by the D flip-flop for one clock cycle and then input into the adder as an addend for the next addition operation, thus realizing The local sequence is cyclically accumulated with the input sequence. The accumulated sum sent to the threshold detector is compared with the set threshold. If it is lower than the threshold, the address generation enable and synchronization indication output are invalid and are '0'. If it is higher than the set threshold, both signals are set high. The subsequent symbol comparison unit starts working to compare the input sequence and the local sequence. The address generated by the address generator consists of two parts, namely:
　　　　　　　address output = accumulated address + offset address.

　　The initial values ​​of both addresses are '0'. The accumulated address counting range is the same as the length of the m sequence. Each clock cycle adds 1. The m sequence output in the first cycle starts from the first symbol. After adding an m sequence cycle, the address generator checks the address generation control signal input by the threshold detection. If the signal is '0', then It means that the input sequence is not synchronized with the local sequence, and there is a phase difference. At this time, the offset address is increased by 1, and the accumulation address restarts the cumulative counting, so that the m sequence output in the second cycle starts to be output from the second symbol, realizing local The "sliding" of the m sequence relative to the input sequence.

　　After the sliding of the local code, it is completely synchronized with the input sequence. According to the correlation of the m sequence, a correlation peak will appear in the accumulated value, exceeding the threshold value of the threshold detection. At this time, the threshold detection unit will set the address generation control signal to '1 ', the offset address of the address generator no longer changes, the accumulated address continues to count cyclically, and the m sequence buffer outputs the m sequence synchronized with the input sequence to the threshold detection unit and symbol comparison unit according to the input address. At the same time, after The UART sends a message to the host PC to start the error test.

　　After the sequence synchronization is completed, the threshold detection unit continues to work to check the synchronization status of the sequence. When at a certain moment, the correlation peak value is lower than the threshold, it can be judged that the system bit error rate is too high, or frame loss occurs during data transmission. At this time, the threshold detection unit invalidates the synchronization indication and address generation enable at the same time, starts a new round of capture, and at the same time sends an alarm to stop the error test to the main control PC via UART, waiting for the start of the next statistics. It can be seen that a corresponding relationship can be established between the design indicators of the system error performance and the threshold in the threshold detection unit, which facilitates parameter setting before testing. Figure 4 is a timing simulation diagram of test code capture. In order to test the error statistics function, we invert the first three codes of the test code to form error codes. As can be seen from the figure, when the sum of the accumulator is higher than the threshold, the synchronization indicator is high. When a new test code cycle begins, the error counting starts. The first three test codes are wrong. You can see the error The code count accurately counts the number of error codes.
　　The symbol comparison unit performs a bit-wise XOR operation on the received sequence with the locally generated m-sequence, and outputs a count pulse every time a bit error occurs. According to the preset parameters, the error counting unit transmits the number of error codes to the computer through UART every time it detects two test code cycles, so that the main control computer can count the error information.

　　The error test unit communicates with the PC through UART and sends the error information to the PC. The PC performs analysis and statistical processing of the error data and forms a report. UART? The baud rate of 57.6Kbps is obtained by dividing the 10MHz clock provided by the system.

3.3 Implementation of real-time display of bit error rate
　　The real-time display of the bit error rate is realized through four common cathode seven-segment digital tubes. It is mainly used when the bit error tester works away from the main control computer. This error rate is calculated through error statistics for every two test code cycles. The real-time bit error rate of the period is displayed on the seven-segment digital tube using scientific notation to conduct a qualitative analysis of the operation of the communication system. The first digital tube displays the units digit and the decimal point, the second digital tube displays the first decimal place, the third displays the negative sign, and the fourth displays a single digit, indicating the negative power of scientific notation. The following takes 256 bit errors counted in two test code cycles (1024 codes) as an example to explain how to obtain real-time display. First, send the number of bit errors to the comparator and compare them with 11 and 102 respectively. 256 is greater than 102, indicating that the bit error rate is in the order of 10 1. The ^fourth digital tube displays 1, and then 1/10 ¹ × 256 = 2560 =
(1010 0000 0000) Take out the 12th and 11th digits of _{2 , that is (10) 2} = 2. As the single digit displayed by the first digital tube, take out the 10th, 9th and 8th digits. bit, that is, (100) ₂ is 0.5 calculated as a binary decimal, then the second digital tube displays 5. When calculating the decimal part, the table lookup method can be used to directly obtain the output value to simplify the calculation.

3.4 Design of software testing platform
　　We use Visual C++ and matlab hybrid programming to implement the software testing platform. Visual C++ is a powerful software development and debugging tool launched by Microsoft. It is very convenient for low-level computer operations. Programming serial ports through API functions is a very mature technology. Matlab is a scientific computing software released by Math Work Company. It has powerful drawing functions and a rich function library, providing powerful support for data analysis and chart production. The basic idea of ​​the software testing platform is to use Visual C++ to compile the human-computer interaction interface of the platform, complete data communication with the error code test core, and then call the functions in matlab to analyze and output the obtained test data. At the same time, in the human-computer interaction The error event and its occurrence time are displayed on the interface.

4. Conclusion
　　This article proposes a design and implementation plan for a bit error rate tester based on FPGA, which is small in size, low in cost, and flexible in use. It exchanges data with the host computer through the built-in UART and takes advantage of the high speed of FPGA. With the advantages of strong computer data processing capabilities, it has achieved better system performance and can be easily used in the development and testing of communication equipment.

　　At the same time, using the online programmability (ISP) capability of FPGA, it can be continuously upgraded and improved to achieve more functions. On this basis, the system can be further expanded, such as adding a microcontroller and transplanting an embedded operating system, replacing the digital tube with a dot matrix liquid crystal, and adding external storage (flash, RAM, etc.) to form a handheld error code The test system can work completely separate from the main control computer.

References:
[1] Chu Zhenyong, Weng Muyun FPGA design and application, Xi'an University of Electronic Science and Technology Press
[2] Zhang Zhiyong and others are proficient in MATLAB version 6.5, Beijing University of Aeronautics and Astronautics Press
[3] CycloneFPGA Family Data Sheet, Altera, March 2003, ver1.1
[4] He Qiang, He Ying MATLAB Extended Programming Tsinghua University Press