Design of high-speed PCI data acquisition card based on CY7CO9449

Abstract: This paper discusses the hardware and software design of a high-speed PCI data acquisition card based on CY7C09449, focusing on the logic programming of the FPGA chip and the driver programming under WindowsXP. The logic design of the FPGA focuses on the design of the synchronous transmission control logic of the CY7C09449 local bus. This logic supports the burst transmission of the local bus and can achieve a local bus data transmission speed of up to 200Mb/s. The driver design of the acquisition card under WindowsXP focuses on the design of the DMA data transmission method, which can achieve a higher speed. The design meets the expected technical indicators and the data acquisition card acquisition speed reaches 80Mb/s.

0 Introduction

Data acquisition is developing in two directions: high precision and high speed. High-precision data acquisition depends on the precision of A/D devices, while high-speed data acquisition depends not only on the speed of A/D devices but also on the design of the data acquisition system. High-speed data acquisition can be divided into two categories according to whether it can be acquired continuously. The first category is high-speed data acquisition within a period of time. The length of time for acquiring data depends on the size of the RAM memory that stores the data; the other is continuous high-speed data acquisition. The acquired data is stored in a large-capacity memory, generally a hard disk, and the acquisition speed is relatively low. This paper proposes a PCI interface high-speed data acquisition solution belonging to the first category, which can achieve a data acquisition speed of up to 80Mb/s.

1 Hardware Structure

The hardware structure of the high-speed data acquisition card is shown in Figure 1.

The acquisition system uses the AD9248 DAC chip, which can perform analog-to-digital conversion on two analog signals at the same time. Each input can select differential input or single-ended input. Its maximum sampling rate can reach 65MS/s, and the sampling accuracy is 14bit. The data transmission uses the CY7C09449 integrated chip, which realizes data transmission between the local bus and the PCI bus. An FPGA connects the CY7C09449 and the AD-9248. The FPGA has two functions. One is to control the A/D chip to realize data conversion, and the other is to interact with the PCI interface chip to realize data transmission.

In terms of hardware design, CY7C09449 and PCI bus are seamlessly connected, the local bus of CY7C09449 is connected to FPGA, and the data line and control line of AD9248 are connected to FPGA. Software design includes the logic design of FPGA device, the driver design of high-speed data acquisition card under WindowsXP and the application software design. This article mainly introduces the software design of high-speed data acquisition card. [page]

2 Data Collection Process

CY7C09449 is a PCI interface control chip produced by Cypress Corporation of the United States. It supports PCI2.0 protocol and can be used as the master device of PCI bus or the slave device of PCI bus. The local bus of CY7C09449 can be directly connected to a variety of commonly used microprocessors. The 128kbit dual-port SRAM shared storage area contained in it can be accessed from PCI bus or local bus, which is its most important resource. Some configuration registers contained in it can be accessed from PCI bus or local bus. On PCI bus, CY7C09449 can be in the position of slave device and receive the host's access to its configuration register or shared storage area. On PCI bus, CY7C09449 can also be in the position of master device and actively initiate data transmission, and transfer data out or store data in shared storage area. It can generate any 32-bit PCI bus address and can initiate burst transmission of PCI bus. On local bus, CY7C09449 is in a subordinate position, and microprocessor controls the initiative to access it. The local bus of CY7C09449 is essentially a synchronous transmission interface that supports burst transmission. The TMS320VC33 processor connects to the local bus of SCY7C09449 by configuring the internal registers of CY7C09449, and is compatible with the asynchronous access mode of TMS320VC33.

The data acquisition process is initiated by the host. The host application requests data acquisition from the driver. The driver writes the 0 bit of the host control status register of CY7C09449 to change the state of the pin RSOUTD from low level to high level. The FPGA starts a data acquisition according to this signal. The FPGA reads data from the A/D and writes it into the SRAM of CY7C09449. The size of SRAM is 4k double words. The FPGA divides it into two 2k double word blocks and uses them alternately. After writing each block, the FPGA requests an interrupt from the host through the IRQ IN pin of CY7C09449. In the interrupt service program, the host driver configures the source address, destination address, and data length of the data transmission by writing the DMA local base address register, DMA host physical base address register, and DMA length register of CY7C09449, and then writes the DMA control register of CY7C09449 to start DMA transmission. In this way, until all data acquisition is completed, the FPGA stops reading data and is in a waiting state. After receiving the last block of data, the host interrupt service program sends a message to the application to inform that the data acquisition is completed. The application can then process the acquired data or store it on disk.

3 FPGA Logic Design

The function of the FPGA device is to read data from the A/D device and then transmit the data to the dual-port SRAM inside the CY7C09449 through the local bus. The logic programming of the FPGA is carried out under Quatus6.0. The top-level logic design uses the schematic design method to divide the FPGA logic into three modules. The internal logic of each module uses the text design method and is programmed in VHDL language. The logic module inside the FPGA is shown in Figure 2.

The A/D control module generates the control signal of the A/D device, reads data from the A/D, and then writes it into the FIFO. The function of the AD control module is relatively simple and easy to implement.

Because the A/D sampling speed is fixed during data acquisition, but the data transmission is sometimes very fast and sometimes blocked for a short time due to waiting. Therefore, FIFO is necessary to buffer the collected data. The FIFO module is generated by the wizard of Quatus6.0, and only the relevant parameters need to be set. The writing and reading of FIFO uses synchronous interface logic. The storage width of FIFO is 32 bits and its depth is 512.

The local bus control module reads data from the FIFO and writes it into the SRAM of the CY7C09449. The local bus of the CY7C09449 supports synchronous data transmission. Although it is also compatible with asynchronous data transmission, the local bus control module of the FPGA uses synchronous data transmission logic because it can achieve higher data transmission speeds. The local bus of the CY7C09449 supports a maximum clock speed of 50MHz. After a synchronous burst data transmission gives the start address of the read or write, data can be transmitted once per clock cycle. The data bus width of the CY7C09449 local bus is 32 bits, which makes the maximum transmission speed of the local bus reach 200Mb/s.

On the local bus of CY7C09449, FPGA is in a position similar to that of a microprocessor, controlling the initiative of local bus data transmission. In the logic design of FPGA, the logic design of the local bus control module is the key to high-speed data transmission. The logic of synchronous data transmission is much more complicated than that of asynchronous data transmission. The state machine is used in the logic design of the local bus control module. The key to its design lies in the definition of the state of the state machine and the conversion of the state under various conditions. For the sake of simplicity, we will not discuss the multi-block data transmission control and interrupt signal generation logic here, but only introduce the logic of transmitting one data block. [page]

The state machine defines a total of 7 states, and the transition relationship between various states is shown in Figure 3.

Before discussing the working process of the state machine, some signals that affect the state transition of the state machine are explained.

The reset signal is the signal output by the RSOUTD pin of CY7C09449. Its transition from low to high will start the FPGA to perform data acquisition.

The FifoEmpty signal is provided by the FIFO module to indicate whether the FIFO is empty. When it is 1, it means that the FIFO is empty and there is no data to be transmitted. Otherwise, it means that there is data in the FIFO waiting to be transmitted.

The RdyOut signal is a signal provided by the RDY OUT pin of the CY7C09449, which is used to indicate whether the local bus of the CY7C09449 is ready for data transmission. When RdyOut is high, it means that the local bus of the CY7C09449 is ready for data transmission, otherwise it means that the local bus of the CY7C09449 is not ready for data transmission.

The Last signal is used to indicate whether the data to be written is the last data to be written in this burst transfer. This signal is generated by the local bus control module. There is a counter inside the local bus control module. When preparing a burst transfer, the length of the data to be transmitted is placed in this counter. The value of the counter is reduced by 1 for each double-word data transmitted. Last is high level when and only when the counter value is equal to 1. [page]

Now let's briefly explain the working process of the state machine:

When Reset changes from 0 to 1, a data transmission is started. The state machine first enters the T1 write address state.

In the T1 write address state, the state machine stores the start address of the data transmission in the SRAM in the CY7C09449 and sends the relevant control signals to the local bus. After the T1 state, it unconditionally enters the T2 wait state to read the FIFO data.

In the T2 waiting state for reading data, if FifoEmpty=1, it will continue to wait. If FifoEmpty=0, it will enter the T3 FIFO reading state.

In the T3 read FIFO data state, the state machine sends a valid read FIFO control signal. If the data read from the FIFO is the last data to be written into CY7C09559, then it enters state T5, otherwise it enters state T4.

The T4 waiting to write and possibly read state is a very critical and complex state. In this state, there are many signals that affect the behavior of the state machine. In Figure 3, the conditions that determine the next state of the T4 state are marked with serial numbers, and the conditions with smaller serial numbers are given priority. If condition (1) is met, RdyOut = 0, it means that CY7C09449 is not ready for data transmission, so it is still waiting in state T4. If condition (1) is not met, condition (2) is met, FifoEmptV = 1 means that CY7C09449 is ready for data transmission, and the FIFO is empty, so the next state is to enter the T2 waiting to read FIFO data state. If conditions (1) and (2) are not met, condition (3) is met, it means that CY7C09449 is ready for data transmission, and the FIFO is not empty. At the same time, the data to be transmitted is the last data of this transmission, so the next state is to enter state T5 to wait for the last data to be written. Satisfying condition (4) means that conditions (1), (2), and (3) are not satisfied, which means that a piece of data is written to CY7-C09449 and a piece of data is read from FIFO and it is not the last piece of data to be written, so the next state is still T4.

In the T5 waiting state to write the last data, when RdyOut = 0, it means that CY7C09449 is not ready for data transmission, so it needs to continue waiting. Otherwise, it means that the last data can be written into CY7C09449, so the next state needs to enter the T6 idle state.

In the idle state of T6, if Reset=1, it remains in the idle state, otherwise it enters the reset state of T0.

The state machine sends out various control signals in each state. There are Fif0Read signals that control FIFO, Select, Strobe, Write, and Blast signals that control the CY7C09449 local bus. The names of these signals indicate their functions, so I will not go into details here.

The local bus control logic supports burst transmission by using synchronous data transmission control mode, which speeds up the data transmission speed.

4 Driver Design

The operating system used by the PC is Windows XP, and the tools used in the software design and development environment include Windows XP DDK, Driver Studio 2.7 and VC++ 6.0. The following discussion focuses on driver design.

In order to speed up data transmission, the driver uses DMA to read the data in the shared memory area of ​​CY7C09449 into the host's memory.

To use DMA data transfer, you need to apply for a memory space with continuous physical addresses for storing data, and then obtain the physical address of the memory space and the user space address. [page]

First, create the following objects in the header file:

KDmaAdapter m_Dma;

KCommonDmaBuffer m_Buffer;

Then create the device descriptor structure m_MiydeviceDescript in the MyDriveDevice:OnStartDevice(Klrp I) function. The settings of each field of the device descriptor structure are as follows:

Pass the UserSIpaceAddress to the application, and the application can access the memory space where the data is stored.

After each 2k double-word data is transmitted to CY7C09449, FPGA sends an interrupt request to the host through the IRQ_IN pin of CY7C09449. In the interrupt service program of the host, m_Me-morjPhyPhysicalAddress is used to set the DMA3E machine physical base address register of CY7C09449, and then the DMA local base address register and DMA length register are set to configure the source address and data length of the data transmission, and then the DMA control register of CY7C09449 is written to start DMA transmission. After all data blocks are transmitted, the host interrupt service program sends a message to the application, and then the application can access the received data through UserSpaceAddress.

5 Conclusion

In the design of high-speed data acquisition card, FPGA control logic of local bus adopts synchronous data transmission control mode, which makes the maximum transmission speed of local bus reach 200Mb/s. The driver design under Windows XP uses DMA data transmission mode to improve the data storage speed. High-speed data acquisition card can reach 80Mb/s data acquisition speed, and the device

The operation is stable and meets the design requirements.