Based on Multisim: CNC pulse width pulse signal generator

The progress of the times, the development of science, and the improvement of talent standards have put forward higher requirements for more and more people, which is one of the prerequisites for every learning motivation. Therefore, in the face of various designs, we must have a good method of analyzing the system. This design is a pulse width pulse signal generator. Through the transformation of the input signal, the output signal required by the design is obtained, so that the entire design is completed while also completing the entire learning requirements. Through the input signal, according to the input frequency, the input signal controls two different counters, thereby generating a duty cycle output waveform with different frequencies.

Chapter 1 Course Overview

1.1 Overall functional requirements

The overall circuit block diagram of the pulse width pulse signal generator is shown in Figure 1-1. The input pulse signal is used as the clock signal of the BCD plus counter modulo 100. The output value of the counter and the programmable digital control value are compared in the digital comparator. When the counter value is greater than the programmable digital control value, the comparator output A>B terminal changes from "0" to "1", and the comparator output A

Figure 1-1 Overall circuit diagram of CNC pulse width pulse signal generator

Since the counter is connected as a modulo 100 counter, the output frequency is 1% of the input signal frequency, and the output pulse width tw=DTi (D is the programmable numerical control value).

1.2 Design Purpose

Students can use Multisim software to conduct a systematic and reasonable analysis of the course design, thereby achieving the transition from theory to practice and strengthening their grasp of the theory.

1.3 Structural analysis

As can be seen from Figure 1-1, the entire system is composed of several components, so it is only necessary to design each component to achieve the purpose, and then further build the connection between them to complete the design. In addition, it can be seen from the two input pulse signals that there are two different pulse signals that need to be designed, in other words, one is "manual" and the other is "automatic". The "automatic" one is the input pulse signal of the modulo 100 counter, and the "manual" one is the input pulse signal of the programmable numerical control (in simple terms, it is the input signal source of the pulse signal).

Chapter 2 Design of Each Module

2.1 Brief Description

Since there are some problems in the design and some simple tests are also needed, the design is written from simple modules to complex ones, but the design steps are still based on the principles of "bottom-up" and "left to right".

2.2 Pulse width control key

This is different from the input pulse signal in Figure 1-1. It requires manual control of the pulse amplitude through a mouse or keyboard. Since it is not difficult, it is only about how to eliminate the key jitter. Since this key jitter will be automatically ignored in the simulation software, but in order to conform to reality, the simulation software also uses the de-jitter operation. Refer to Figure 2-1. The circuit can convert the input jitter signal into a flat and jitter-free signal through two NAND gates. The principle is similar to that of the RS latch, so the RS latch can be used instead, because there is not much difference between the two. The two NAND gates connected in this way can realize the internal circuit structure of the RS latch.

Figure 2-1 Circuit diagram for eliminating key jitter (Image from the Internet [1])

From Figure 2-1, we can derive the circuit diagram of Appendix I-1, the Multisim software simulation circuit, and then after slight modifications, this aspect of the test (including the circuits of the subsequent modules) will be placed in the third chapter test in order to make the entire document more tidy.

Figure 2-1 is the prototype of the SR latch. As shown in the truth table of Table 1-1, on the one hand, two high levels set one pin in the 74LS00 NAND gate chip to high, so no matter how the key press fluctuates, only one pin can be pulled down to a low level. Therefore, the situation where both the R and S ends of the RS latch are 0 at the same time does not exist, so unstable and unacceptable errors will not occur.

table 2-1

That is to say, when the button is pressed down, there will be jitter in the process from 01 to 10, but no matter how it jitters, its output function is only one, that is, from 0 to 1, so there will be no output jitter waveform.

2.3 Programmable CNC

This aspect involves the circuit involved in 2.2, but it will not be explained here and will be put in Chapter 3 for testing.

The programmable numerical control circuit performs logic operations of adding 1 or subtracting 1 under the control of the pulse control key. It is actually a reversible counter, which uses two decimal add/subtract counters cascaded into a modulo 100 add/subtract counter. Its output data is sent to the corresponding data end of the comparison BCD circuit, and under the action of the key pulse, various digital numbers from 0 to 99 are numerically controlled.

Here, programmable numerical control is the next step in building the pulse width control circuit, and it is also an important part of completing the next step. The addition/subtraction counter is used, and there are many similar addition/subtraction counters in the 74LS series, so only 4029BD is used here. The entire circuit can be referred to in Appendix II-1 circuit diagram.

Figure 2-2 Programmable CNC thinking diagram

The circuit diagram in Appendix II-1 is designed according to the idea of ​​Figure 2-2. From the above, we can know that the pulse width control key serves the clock pulse input end of 4029BD (here refers to the low bit), thereby generating a corresponding level signal to drive two 4029BDs. However, since the 4029BD chip is a circuit chip that combines adders and subtractors, its addition/subtraction logic must be transformed to achieve a "+" or "-" signal response under the level signal transmitted by the pulse width control key circuit.

This part changes the "programmable" part into switch control, making this module independent before assembly. Since the CI port is a carry input port, the "high bit" is controlled by carry, or similar to the "clock control" of the 74LS series, so as to achieve the driving of the high bit. The other pins are not used except for binary/hexadecimal and addition/subtraction operations, so they can be directly set to low level.

2.3.1 Differences between binary and hexadecimal

Since the chip input is divided into binary and hexadecimal, but 4 bits of binary can only represent 1 bit in hexadecimal, that is, to output 4 bits of input signal for 4-segment digital tube, 16 bits of binary signal are required, so hexadecimal is used here. To control the input signal, you only need to connect the pin to a low level, which is different from the previous ones that can be directly connected to a low level. Connecting to a high level will make a huge difference in the output data.

2.4 modulo 100 counter

This is similar to 2.3, but the difference is that 74LS160 is a relatively common 74LS series electronic component, while 4029BD is a component similar to a certain component in the 74LS series. However, the usage is the same. Please refer to the circuit diagram in Appendix II-1.

Unlike the 4029BD chip, it can only do addition but not subtraction, and the carry signal is more complicated, and needs to be connected in a certain way and then input to the "high" CLK clock pulse input pin as a "clock pulse signal". Since the modulo 100 counter does not have any requirements on the base of the adder counter, you can refer to the circuit diagram in Appendix II-2, and the carry signal used is also quite simple.

Table 2-2

As shown in Table 2-2, other pins are not needed and can be directly connected to a high level, thus preventing them from taking effect. The reason is that the chip itself does not work when it is cleared, and the ENT and ENP pins are only required by the designed counter when both are at a high level. In addition, the CLR and LOAD pins are set ports, and the setting methods of the two are very different, one is asynchronous setting and the other is synchronous setting. However, because the two 74LS160 chips just constitute a 100-base counter, that is, a counter with a modulus of 100, the two setting pins only need to be set to a high level. As for the carry, the method mentioned above uses the carry end of the low position as the time pulse output end of the high position, so that the low position can complete a circle, and the high position has just taken a step.

2.5 Duty cycle display

Figure 2-3 Duty cycle display circuit diagram

In Figure 2-3, the signal source is from the programmable digital control circuit to the input of the 4511BD decoder, which results in the circuit diagram in Appendix II-2. In addition, since the seven-segment digital tube is not under the "intermediate resistance" - it cannot be used - it is necessary to provide appropriate circuit protection for the circuit so that the input voltage of the seven-segment digital tube is not too high. Simulation is simulation, so in the actual circuit, it cannot be just 180 ohms, otherwise either the main circuit will burn out or the seven-segment digital tube will burn out! Therefore, protection resistors for two digital tubes are given to ensure stable operation of the program.

2.6 Eight-bit BCD code comparator

Figure 2-4 Eight-bit BCD code comparator

This is the circuit that produces the final waveform after comparing the two "counter" circuits (this waveform is also in Chapter 3), see Appendix II-4 circuit diagram. When receiving the 8-bit digital numbers sent to the comparator by the modulo 100 counter and the programmable digital control circuit respectively, the 74LS85 will compare the two. For example, the number sent by the modulo 100 counter is 90, and the programmable digital control is 30. The binary numbers of the two are 10010000 and 00110000 respectively. The 74LS85 starts the comparison from the high bit, that is, it will compare the next bit only when the highest bit is equal. For example, the highest bit of the modulo 100 counter is 1 and the highest bit of the programmable digital control is 0, so it directly outputs the result of greater than, but when the highest bits of both are 1, it will compare the next bit, and so on.