Taixiang Test 002: Is the "rice skin" fragrant? Brother Shui gives you an in-depth explanation of MIPI testing

MIPI, which stands for Mobile Industry Processor Interface, is a non-profit organization that focuses on developing software and hardware standards to meet the special needs of mobile terminals. MIPI's goal is to simplify the design and application of software and hardware by promoting the consistency of processor and peripheral interfaces , and to improve the reusability and compatibility of mobile devices. MIPI provides specifications for standard hardware and software interfaces in mobile devices, improves the interoperability between components produced by different manufacturers, reduces integration work, and speeds up the product development cycle of mobile terminals.

MIPI Technology Development Trends

MIPI is committed to building signal interconnection in mobile products and automotive electronics. It has been deeply involved in mobile products for many years, especially in video streaming data transmission, and is widely used. There are four physical layer standards in the MIPI Alliance standard, namely D-PHY, C-PHY, M-PHY and A-PHY.

D-PHY is the first standard developed by MIPI. D-PHY is mainly used for video stream data transmission of display interface DSI and camera interface CSI. D-PHY is the most widely used video stream interface in today's smartphones and the most well-known MIPI standard. M-PHY is the second member of the family. M-PHY is mainly used for data transmission. The most commonly used application scenario is UFS. C-PHY is an improved version of D-PHY. Its application scenario is exactly the same as D-PHY. C-PHY is more sophisticated in encoding and has higher data transmission efficiency. A-PHY is the latest version of the automotive serializer-deserializer (SerDes) physical layer interface recently announced by the MIPI Alliance. It is a high-speed standard customized for in-vehicle applications. Before this, MIPI already had a complete set of communication protocols. D-PHY, C-PHY, and M-PHY were widely used in the fields of Camera and Display for physical transmission of large amounts of data. However, these physical layer protocols cannot be transmitted over long distances. A-PHY is designed to provide physical layer support for data transmission across the entire vehicle distance. Its maximum transmission distance can reach 15 meters, and the maximum transmission speed can reach or even exceed 48Gbps in the future, far exceeding the 1.5Gbps of LVDS. A-PHY will help the automotive industry accelerate the performance of advanced driver assistance systems (ADAS), autonomous driving systems, and automotive surround view systems.

MIPI D-PHY Basics

The D-PHY bus includes the DSI and CSI buses for display and camera. D-PHY is different from many existing mobile interfaces. It can switch between differential mode (high speed) and single-ended mode (low power) in real time, depending on whether a large amount of data needs to be transmitted or power needs to be saved. The D-PHY interface can operate in a simplex or duplex configuration, supports one data path or multiple data paths, and can flexibly provide the required link. D-PHY uses a pair of source-synchronous differential clocks and 1 to 4 pairs of differential data lines for data transmission. Data transmission adopts DDR mode, that is, data is transmitted on the upper and lower edges of the clock.

Detailed video explanation of D-PHY Tx physical layer signal measurement.

Physical layer standards: Specifications of the Camera CSI interface and the Display DSI interface.

There are two transmission modes: high speed (HS) and low power (LP). In HS mode, low voltage differential signal is used, which consumes more power but can transmit very high data rate and support voltage range of 100mV to 300mV. In LP mode, single-ended signal is used, which has very low data rate and power consumption and supports signal level of 0V to 1.2V. The combination of the two modes ensures that the MIPI bus can transmit at high speed when large amount of data needs to be transmitted, and can also be in low speed mode to reduce power consumption when large amount of data is not needed.

The transmission modes are mixed and alternated in actual applications: the signal is constantly switched between LP and HS;

Maximum data rate: High Speed ​​mode, 80Mbps to 4.5Gbps; Low Power mode, Up to 10Mbps.

Bus termination: 50 ohm, high speed HS mode; Hi-Z high impedance, low speed LP mode.

MIPI D-PHY Timing

1. During operation, LP and HS modes appear alternately; LP and HS have different levels, different termination resistors, and different data rates;

2. The main function of LP is to save energy. When idle, D-PHY will be stable in LP11, and the power consumption is extremely low in the constant voltage state; the main function of HS is data transmission, using differential low voltage to transmit signals, using Double Data Rate (Data: Clock=2:1);

3. In the LP state, Data+ and Data- can be in the same logic state. For example, from LP to HS, it will go through three states: LP11 -> LP01 -> LP00. In LP11, Data+ and Data- are both at a high level, and in LP00, they are both at a low level.

4. Clock has two different configurations: Continuous and Normal. The former is simpler in design, while the latter is more energy-efficient.

What is C-PHY?

The C-PHY transmitter has three signal voltage heights: High, Mid, and Low. The receiver calculates the difference between AB, BC, and CA for decoding and recovers the clock. C-PHY has five possible state transitions. Unlike D-PHY, which uses 0 and 1 levels to represent encoding, C-PHY uses state jumps to represent encoding. The data that can be encoded for each symbol is log25 = 2.3219 bits/sym. The theoretical bandwidth is 2.3219 times that of D-PHY, and the encoding efficiency is greatly improved.

MIPI D-PHY and C-PHY Timing Comparison

D-PHY is a source synchronous system with a synchronous clock channel, while C-PHY does not have a synchronous clock and the clock is embedded in the data. The physical layer structures of D-PHY and C-PHY are different. From the line point of view, C-PHY is a three-wire system of A, B, and C. Since MIPI C-PHY does not transmit the clock, the CDR needs to recover the clock first, and then use the recovered clock to sample the data and find the synchronization header.

MIPI D-PHY Test Challenges

MIPI D-PHY bus works in two working states: LP and HS: LP (Low Power) state, the maximum working rate does not exceed 10Mbps, the signal swing is 1.2V, and the termination impedance is high impedance; HS (High Speed) state, the working rate ranges from 80Mbps to 4.5Gbps, the signal swing is 200mV, and the termination impedance is 50 ohms. Due to the difference in signal swing, the dynamic range required for D-PHY signal testing is higher, and its tolerance to noise is lower. In actual testing, the signal quality may not be ideal, as shown in the figure below.

Difficulties in MIPI signal testing

1. CTS has many measurement items: 64 for D-PHY, 41 for C-PHY

2. Signal integrity and corresponding timing in two completely different working modes: HS and LP

3. Measure by welding the probe

4. Measurement accuracy: Use reliable algorithms to filter out specific waveforms and perform precise measurements

5. The measured waveform is sometimes very poor

6. Automatically detect the transition edge and measure items

7. Minimize probe loading effects

8. The density of the board is getting higher and higher, and the test points are difficult to solder.

9. Automatic test settings, adapt to HS and LP modes

MIPI D-PHY Decoding

In actual debugging projects, engineers usually need to find the reason why the equipment is not working properly. This requires not only consistency testing of the D-PHY physical layer signal, but also serial triggering and decoding functions for the D-PHY signal. The following are the D-PHY signal decoding, synchronization and error alarm, and protocol event list export functions, which greatly facilitate the development and debugging of D-PHY signals.

D-PHY Tx Signal Test and Connection Diagram

For the test of MIPI D-PHY multiple differential buses , three or four probes are needed to complete the detection of data and clock signals. If the clock is a continuous clock, at least three probes are required to complete the detection. If the clock is a Normal non-continuous clock, four probes are required to complete the test; then use the D-PHY Tx physical layer consistency test software to complete the fully automated test.

In most cases, the connection method shown in the lower left figure is used. The object under test is a complete system, which includes the D-PHY controller and device. The probe connects to the object under test and measures the signal quality without destroying the working state of the system. If the chip under test, the connection method shown in the lower right figure may be used. The chip measures the signal quality through the evaluation board. There is only one D-PHY controller chip and some peripheral circuits, and the signal is led out through the SMA connector on the evaluation board. A termination board is required to provide dynamic termination of D-PHY on the evaluation board, and the probe is connected to the test point on the termination board for signal observation.

D-PHY Measured Eye Diagram

C-PHY Measured Eye Diagram

D-PHY Tx Physical Layer Test Reference Configuration

summary

The MIPI D-PHY Tx physical layer signal consistency test requires the use of three or four probes to complete the detection of data and clock signals, and then uses a real-time oscilloscope and D-PHY Tx physical layer consistency test software to complete the fully automated test, which improves the test efficiency, thereby helping engineers to quickly verify products and accelerate the process of product marketization.