ACS integrated test system based on high throughput WLR test

Figure 4. TDDB testing using a shared SMU architecture on the left and an SMU-per-pin architecture on the right.

NBTI testing presents different issues. The NBTI test structure is a MOSFET where stress is applied to the gate and measured at the drain, with the source and substrate grounded. NBTI requires very high measurement speeds due to degradation recovery issues. The stress interruption time for characterization should be kept as short as possible. The faster the measurement speed, the more accurate the degradation measurement. 2 Obviously, a shared SMU system introduces a delay between the stress and measurement cycles, and introduces variability in the stress duration between characterizations. Even when using potentially damaging thermal switching techniques3, variations in stress cycle lengths must be measured and accounted for during lifetime analysis.

Parallel testing and multiple groups of parallel testing improve the utilization of testers and probes and increase throughput by measuring multiple devices simultaneously. The increased throughput can be several times that of the sequential test flow shown in Figure 5 relative to standard reliability testing.

For simple tests consisting of only stress-measure sequences, a shared SMU approach can reduce test time with faster sources, shorter settling delays, and higher integration rates. This comes at the high cost of increased measurement error. Another parallel testing approach can provide test results for four devices in the time it previously took to test one. Of course, this assumes that the test time is much longer than the overhead (e.g., probe movement). Increasing the number of devices under test, especially in longer reliability tests, can save significant time and provide more statistical data samples.

Figure 5. Time difference between sequential and parallel testing

Implementation of Parallel SMU-per-pin ACS Integrated Test System

Using multiple GPIB groups of Series 2600 SourceMeters enables parallel testing of the ACS integrated test system. Typically, a group of 4 SMUs (2 Series 2600 instruments) is used to measure a 4-terminal FET or 4 capacitors. The Series 2600 instruments in the group are connected using TSP-LinkTM and controlled as a single instrument. This approach enables system scalability and simplifies test management within the ACS. Therefore, multiple groups of SMU-per-pin test systems can be established. For parallel testing, the test script is preloaded into each 2600 host and saved in its memory. When triggered, the controller will initiate a function call to each group's host, which will run the script to coordinate the other 2600 instruments. The controller then scans the bus and receives test results from the 2600 host.

Figure 6. Example of a setup for multiple groups of Series 2600 instruments connected using GPIB and TSP-Link. Each group starts running a script (same or different) at the same time.

in conclusion

Increased time-to-market and test cost pressures mean test engineers must do more with less. Leveraging Keithley's proven instruments and measurements, the ACS Integrated Test System fills the gap between interactive lab-based tools and high-throughput production test tools. The ACS system shown in Figure 1 represents an SMU-per-pin configuration that is very beneficial for miniaturized CMOS reliability testing. Engineers using this system have great system flexibility and throughput, providing not only a huge amount of statistical data, but also excellent performance of individual device measurements.