Fault Diagnosis of Hybrid Circuits Based on Current Testing

　　0 Introduction

　　With the rapid development of electronic technology and the continuous improvement of manufacturing technology, the complexity of circuits has continued to increase, and the chip size has been reduced, so that more and more mixed signal circuits are integrated on the system-level chip, rather than just digital circuits or analog circuits. Due to the different test methods for digital and analog circuits, traditional testing can no longer meet the needs of development, which has brought unprecedented challenges to the designers, users, and maintainers of instruments and equipment, and has also made the detection of digital/analog mixed signal circuits increasingly highly valued by industry insiders. The mixed circuit fault diagnosis based on current testing proposed in this paper is proposed in this context.

　　1 Theoretical knowledge of current testing

　　Current testing refers to the detection and location of circuit faults by measuring the power supply current and effectively extracting the fault information of the circuit from it. It includes static current testing technology IDDQ and dynamic current testing technology IDDT.

　　When the circuit is working normally, the static current is very small, but the static current of the defective circuit is very large, so when the static current in the circuit is detected to be abnormal, it can be determined that the circuit has a fault. This is also the principle of IDDQ testing. However, some faults in CMOS circuits, such as open circuit faults, do not cause abnormal static current. Therefore, it is necessary to introduce dynamic current testing. Based on this, this paper considers the combination of static current and dynamic current testing, rather than simply static current testing. IDDT is a short-term conduction current, that is, during the state transition of the CMOS circuit, the PMOS transistor and the NMOS transistor are turned on at the same time, so that a conduction circuit is formed between the power supply and the ground, as shown in Figure 1. Since IDDT is the change of current in the circuit during the dynamic transition, the size of IDDQ does not affect its result. Therefore, this also avoids the impact of the growing static leakage current of deep submicron circuits on the test. This paper studies the important significance of the combination of the two in hybrid circuit fault diagnosis.

　　

　　2 Wavelet Neural Network for Hybrid Circuit Fault Diagnosis

　　Wavelet Neural Network is a combination of wavelet analysis theory and artificial neural network ANN theory. At present, there are two ways to combine the two:

　　(1) Loose combination. That is, wavelet analysis is used as a pre-processing method for neural networks to provide input feature vectors for neural networks.

　　(2) Compact combination. Wavelets and neural networks are directly fused, that is, wavelet functions and scaling functions form neurons.

　　This paper adopts a loose combination of wavelets and neural networks. First, the normal circuit and the fault circuit are modeled and simulated by PSPICE, and the static current IDDQ and dynamic current IDDT parameters are extracted. Wavelet analysis is used in Matlab to extract the characteristics of the obtained current, and a specific analysis is performed in combination with the neural network. The steps are as follows:

　　(1) Parameter extraction. The current information of the normal circuit and the circuit with various faults such as bridge faults and open circuit faults is extracted in PSPICE.

　　(2) Wavelet analysis. The current information obtained in (1) is decomposed by wavelet in Matlab, the wavelet coefficients are extracted, and the RMS is further calculated.

　　(3) Fault location. The wavelet analysis is combined with the BP neural network to analyze and judge its location effect. The specific steps are shown in Figure 2.

　　

　3 Hybrid circuit fault diagnosis example

　　In PSPICE, a hybrid circuit composed of 7404 and a common collector amplifier circuit is used to study the fault model. The circuit model is shown in Figure 3. Through sensitivity analysis, it can be seen that R1, R2, R5, and C1 have a greater impact on the circuit. Four bridge faults and four open circuit faults are set in the circuit, as shown in Table 1. Although the production process leads to various circuit defects, various fault models can be used to equalize them according to the failure mechanism of various defects. For bridge faults, this paper uses a resistor connected between the bridge points to establish a fault model, and the resistance values ​​are 10 Ω, 1 kΩ and 1 MΩ to correspond to relatively small, approximately equal, and relatively large. For open circuit faults, a 10 MΩ point resistor is connected to the open circuit point to establish a fault model.

　　

　　

　　3.1 Application of IDDQ in hybrid circuit fault detection

　　By simulating each fault model in PSPICE, the static current value can be easily obtained. IDDQ can clearly see the difference in leakage current for bridge faults in hybrid circuits, but it cannot detect open circuit faults. [page]

　　3.2 Application of IDDT in hybrid circuit fault detection

　　For the dynamic current information of normal circuits and open circuit faults obtained in PSPICE, a 5-layer wavelet transform is performed in Matlab to obtain the wavelet coefficients. The root mean square error is then used to reflect the difference between them. The root mean square error is defined by formula (1):

　　

　　Where: Fi is the wavelet coefficient of the open circuit fault; Gi is the wavelet coefficient of the normal circuit; N is the number of wavelet coefficients. The RMS value is obtained by formula (1), see Table 2.

　　

　　Therefore, through the analysis of the previous two sections, it can be seen that the combination of static current test and dynamic current test can significantly improve the fault coverage of the hybrid circuit, which has a certain guiding significance for the future diagnosis of hybrid circuit faults.

3.3 Combination of wavelet feature extraction and BP neural network

　　(1) Extraction of energy features. The current information of the circuit is decomposed by 5 layers of wavelets to obtain high-frequency wavelet decomposition coefficients and low-frequency wavelet decomposition coefficient vectors (d5, ..., d1, a5). Among them, the extraction of high-frequency coefficients uses the detcoef function in Matlab, while the extraction of low-frequency coefficients uses the appcoef function. Then combine the coefficient vectors into an energy feature vector:

　　F = (Ed5...Ed1, Ea5)

　　(2) Determine the structure and parameters of the BP neural network. The number of input neurons of the BP neural network is determined by the test node; the number of hidden layers can be roughly estimated by the "trial and error method" and formula (2).

　　In the formula: m, n and l are the number of hidden layer nodes, input nodes and output nodes respectively; a is an uncertain number between 1 and 10.

　　After repeated experiments, the BP neural network results of this paper are 6-7-4.

　　(3) Training the BP neural network. During the circuit simulation, 20 Monte Carlo analyses are performed to generate 20 samples, 10 of which are training samples and the other 10 are test samples. A total of 4 groups of training are required in this paper. The network training error curve is shown in Figure 4. It can be seen from the figure that the network has reached the target error after 4432 steps of training.

　　

　　(4) Test the BP neural network to verify the trained BP neural network. The results are shown in Table 3. The detection rate of the wavelet neural network in this paper reaches 95%.

　　

　　4 Conclusions and Prospects

　　Traditional fault diagnosis methods such as fault dictionaries, sensitivity-based analysis methods, and sub-network tearing methods can solve some tests and diagnosis. However, with the widespread application of mixed-signal circuits, high reliability has put forward higher requirements for fault diagnosis. Through this project, we first learned that the combination of static current testing and dynamic current testing can significantly improve the fault coverage of hybrid circuits; secondly, the combination of wavelet neural networks is significantly better than the single neural network method for fault location. From the latest literature, we can also clearly know that combining two or more fault diagnosis methods has become a development trend in hybrid circuit fault diagnosis.

　　Although this project has improved the fault diagnosis rate of hybrid circuits, the production of test vectors, unified modeling of hybrid circuits, and unified analysis of test responses are still severe challenges for hybrid circuit fault diagnosis.