Design of broadband impedance meter——Microprocessor circuit design (II)

5.3 Human-machine interface unit circuit

In order to facilitate the expansion of the system and meet the needs of human-computer interaction, this design provides an LCD display interface, keyboard control, etc., and also provides an RS-485/232 communication interface. The LCD display interface is used to display the test results, which can be displayed in character and graphic form; the keyboard control is used to set some parameters to obtain the changes in the test results under different conditions; the RS-485/232 communication interface is used to realize information communication and sharing with other monitoring equipment or external computers. The

schematic diagram of the human-computer interface unit is shown in Figure 5-5.

5.3.1 RS232/485 interface circuit design

The system is equipped with two universal asynchronous serial ports, and the interface standard configuration is 1 RS232 and 1 RS485, which can be used to communicate serially with computers and other devices. The design directly uses the 2-channel SCI on the F2812 chip as the asynchronous serial transceiver UART.

The TMS320F2812 chip integrates the SCI module, which is a two-wire asynchronous serial port. The SCI module supports digital communication between the CPU and asynchronous peripheral devices using the non-return to 0 (NRZ) standard format. The receiver and transmitter of the SCI each have a 16-level deep FIFO, and they also have their own independent enable bits and interrupt bits, which can be operated independently in half-duplex communication, or simultaneously in full-duplex communication. The SCI

module structure diagram is shown in Figure 5-6.

Compared with the previous DSP SCI, the SCI of TMS320F2812 has two characteristics: first, both transmission and reception have independent FIFOs; second, the baud rate can be automatically detected. The automatic baud rate detection logic mainly solves the problem of determining the terminal baud rate during the communication process. And its 16-word FIFO can greatly reduce the number of communication interruptions and increase the communication rate. The SCI of TMS320F2812 has 4 external pins: SCIRXDA, SCITXDA, SCIRXDB, SCTTXDB. When not communicating, these pins can be used as general I/O. SCI has a 16-bit baud rate selection register. By changing the value of the register, more than 65,000 baud rates can be obtained.

This design configures the on-chip SCIA module as a 1-way RS232 serial port, and the interface level is configured as the RS232 interface level standard. The on-chip SCIB module is configured as a 1-way RS485 serial port, and the interface level is configured as the RS485 interface standard. RS485 is a half-duplex serial communication. The receiving and sending share a line. The receiving and sending of RS485 are controlled by PB12 of GPIO of F2812. When PB12 level is high, RS485 is in sending mode. When PB12 level is low, RS485 is in receiving mode. [page]

RS232 uses SP202EEN of Sipex Company, RS232 serial bus transceiver. This chip has the characteristics of low power consumption and high transmission rate. It works at 5V working voltage and meets all RS232D and ITUV.28 standards. The circuit schematic is shown in Figure 5-7.

The RS485 interface uses TI's SN65HVD485E bus transceiver [33-35]. This chip is also powered by +5V and fully complies with the TIA/EIA RS485A standard. It is suitable for data transmission up to 10Mbps over long twisted pair cables and has an electrostatic protection level of 15KV. The circuit schematic is shown in Figure 5-8.

5.3.2 USB interface circuit

The designed USB bus has the characteristics of high transmission speed, hot plug, plug and play, etc., and is currently widely used. In order to facilitate the communication between the system and external devices, this design also designs a USB interface.

The system uses Cypress's CY7C68001 chip to implement the USB2.0 interface. The CY7C68001 universal USB2.0 interface controller is an interface device based on application layer programming. Compared with other interface devices based on link layer programming, it is simple to use and easy to develop. The CY7C68001 integrates the USB2.0 transceiver (physical layer) and the USB2.0 serial interface engine SIE (link layer, implementing the underlying communication protocol). As a peripheral of F2812, the USB application layer protocol is implemented by F2812 programming. CY7C68001 uses a parallel asynchronous memory interface to connect to F2812. The host can wake up F2812 and configure USB.

CY7C68001 complies with USB2.0 specification; supports high-speed (480Mbps) or full-speed (12Mbps) USB data transmission; 4 programmable endpoints share 4KB FIFO, and the FIFO space size and FIFO status corresponding to each endpoint are programmable; 8/16-bit bidirectional command interface, flexible configuration (synchronous/asynchronous configurable, status pin, read/write pin and polarity programmable), data I/O port can communicate with DSP, FPGA or other ASIC synchronously/asynchronously; intelligent SIE function (enumeration can be completed without the help of microprocessor interruption); integrated phase-locked loop function; I/O port is 3.3VTTL level, can withstand 5V voltage.

The interface circuit of TMS320F2812 and CY7C68001 is shown in Figure 5-9.

The relevant pin descriptions of CY7C68001 are as follows: FD[01:016] pseudo data bus, FA[0:2] address line and CS chip select signal together constitute the address space of CY7C68001. In addition to the memory interface, CY7C68001 also has 1 interrupt signal USBINT and 4 status signals (READY, FLAGA, FLAGB and FLAGC). The USBINT signal indicates that an interrupt event has occurred in CY7C68001, or reflects the end of the read operation for CY7C68001; FLAGA, FLAGB, and FLAGC report the FIFO status selected by FIFOADR[2:0], which correspond to the FIFO custom, full, and empty states by default; FLAGD is the FIFO status chip select and optional, and the default is the chip select signal; SLOE is the CY7C68001 driving parallel data bus, which is often short-circuited with SLRD; SLRD is the parallel port read valid signal. When SLRD is valid and synchronous communication is in progress, the FIFO pointer increments at each rising edge of IFCLK; SLWR is the parallel port write valid signal. When SLRD is valid and synchronous communication is in progress, the FIFO pointer increments at each rising edge of IFCLK; the PKTEND signal is always high, submitting the current buffer to the host computer USB. [page]

5.3.3 Display circuit and keyboard interface circuit design

The display circuit design uses a CM12864-10 LCD with a built-in T6963C controller. The

CM12864-10 graphic LCD module consists of a controller T6963C, a column driver T6A39, a row driver T6A40, and an interface with external devices. It can display characters (including Chinese and Western characters), graphics, and a mixture of characters and graphics. The control and drive of the LCD display are completed by the chip and circuit inside the module, so the only connection with the outside is the data line and the control line. The CPU sets the required display mode through these data lines and control lines, and other functions are automatically completed by the module.

DSP and LCD interface circuit design:

For the dot matrix LCD interface, the read/write access is performed through an 8-bit command port and an 8-bit data port. In this design, the LCD interface is allocated in the Zone 0 space of F2812, occupying 2 address units: 0X002800, the data port of the LCD interface: 0X002801, the command port of the LCD interface. The

interface signals between F2812 and LCD are as follows:

LCD_D[7:0]: 8-bit data bus

LCD CE: Chip select signal

LCD I/D: Command/data selection signal

LCD RD: Read signal

LCD WE: write signal

LCD RST: Reset signal

LCD LIGHT: Backlight control signal

The connection between LCD and F2812 is shown in Figure 5-10.

The design uses a 4×4 keyboard interface, using F2812's PB[15:12] as the 4 keyboard scan output lines, and F2812's PA[10:7] as the 4 keyboard scan readback lines. The keyboard scan, readback, debounce and other timings are implemented by software programming.

5.4 Boot loading and reset circuit

5.4.1 Boot Loading Mode Selection

TMS320F2812 has two program loading modes, namely microprocessor mode and microcomputer mode [39]. When the system is started or in the reset process, the value of the external pin XMP/MC is sampled and locked into the XINTF configuration register XINTFCNF2. The reset state of this pin determines whether it is loaded from the Boot ROM or the external XINTF Zone 7. If XMP/MC = 1 (microprocessor mode) during reset, Zone 7 is enabled and the reset vector is booted from the external memory. If XMP/MC = 0 (microcomputer mode), the Boot ROM is enabled and the XINTF Zone 7 is not enabled. In this case, the reset vector is booted from the internal Boot ROM.

In this design, the microcomputer mode is used, that is, the system is booted from the Boot ROM. The Boot ROM is the internal boot ROM of F2812, and the address is 0X3FF000h~0X3FFFC0h. TI has loaded the product version number, released data, checksum information, reset vector, CPU vector table (for testing) and math table into this memory. The main function of Boot BOM is to realize the Bootloader function of F2812. When the chip leaves the factory, the manufacturer's bootloader is installed in the 0X3FF000h~0X3FFFBFh memory of Boot BOM.

5.4.2 Reset mode and reset source

The impedance meter is designed with four reset sources: power-on reset, manual reset, watchdog reset and power monitoring reset. Any effective reset will cause the entire system to reset.

When the F2812 is reset, all current operations are terminated, the CPU enters a known initial state, the pipeline operation is refreshed, all CPU registers are reset, and the state of related signals is reset. After the reset is completed, the CPU takes the reset vector from 0X3FFFC0H to the PC register and then starts executing the program. If the XMP/MC pin is low, the high 16K×16 bits of the program space are mapped to the on-chip Boot ROM, and 0X3FF000H is stored in the 0X3FFFC0H unit of the on-chip Boot ROM, that is, the program will start executing from 0X3FFC00H of the on-chip Boot ROM, and the 1K×16-bit storage space starting from 0X3FFC00H in the on-chip Boot ROM is the BootLoader program. If the XMP/MC pin is high, the upper 16K×16 bits of the program space are mapped to Zone 7 off-chip. When designing, the CPU interrupt vector table should be stored at 0X3FFFC0H in Zone 7.

5.4.3 Watchdog Circuit

In the design, XMP/MC is pulled down to make F2812 work in MC mode. After power-on, the program is executed from the on-chip Boot ROM. The Jump to Flash Boot mode is selected, and GPIOF4 is pulled up on the chip. The program will jump to 0X3F7FF6H of the on-chip Flash. The jump instruction is stored in 0X3F7FF6H and jumps to the actual application. The application first initializes the PIE interrupt vector table and then enables PIE. When using the Jump to Flash Boot mode, the on-chip watchdog circuit is not stopped, so the watchdog circuit should be refreshed within the specified time, otherwise it will cause the watchdog to overflow and generate a reset.

The watchdog reset directly uses the watchdog circuit on the F2812 chip. The watchdog circuit on the F2812 chip is an 8-bit add counter. When it counts to the maximum value and overflows and flips, a reset pulse or interrupt request output will be generated. The input clock of the adder can be selected by the WDCR register, so that the action cycle of the watchdog circuit can be programmed within a certain range; in addition, by sequentially writing 0X55+0XAA to the WDKEY register, the adder is cleared to 0, so as long as 0X55+0XAA is periodically written to the WDKEY register within the overflow cycle, the watchdog circuit will not overflow. In addition, the watchdog circuit can be disabled through WDCR. The

manual reset and monitoring circuit is shown above, using TI's TPS3823-33DVBT chip, which is used to monitor the power supply voltage and manual reset system, which has been introduced in detail above.