Design of flow measurement system based on eddy current flow sensor

1. Hardware circuit

As shown in Figure 13 , the design principle diagram of the flow measurement system based on the eddy flow sensor is shown. In this experiment, we use P1.0 as the input and connect it to the output of the eddy flow sensor . In order to improve the measurement accuracy of the flow, we use P0 and P2 as the frequency multiplication input. Under different flow conditions, we choose different frequency multiplication. Obviously, when the measured flow is large, the frequency multiplication we choose will be reduced accordingly, and the accuracy will be reduced accordingly; vice versa. In this experiment, we use P1.7 only to verify whether the frequency multiplication is correct.

Figure 12 Schematic diagram of flow measurement system design based on eddy current flow sensor

2. Circuit Principle

Specific implementation process:

(1) Use the level change of the P1.0 signal and timer T0 to measure the period of the input signal: Set timer T0 to mode 0 timing. Before the rising edge of P1.0 arrives, start timer T0 to start counting the internal clock. After the next rising edge of P1.0 arrives, turn off timer T0 and read the count value M to start the next timing process. The input signal period is:

(4) The output signal should not only be frequency-multiplied, but also be in phase with the input signal, that is, the rising edge of the frequency-multiplied output signal should appear at the same time as the rising edge of the input signal. In analog circuits, automatic phase synchronization is achieved by a phase-locked loop circuit, which gradually achieves the synchronization purpose by phase detection and closed-loop adjustment of the input and output signals. In digital circuits, synchronous phase locking can be achieved by controlling the starting point of the output signal relative to the input signal. To this end, synchronization takes one input signal cycle as a period. At each rising edge of the input signal, timer T1 is started and P1.7 outputs a high level. After timer T1 generates (2N-1) timing interrupts, timer T1 is turned off and P1.7 outputs a low level, waiting for the synchronization moment of the next period.

3. Experimental Procedure

Figure 13 Phase-locked frequency multiplication Program flow chart

To summarize, the flow rate Q measured by the eddy current flow sensor is the pulse frequency f0 output by P1.7 divided by the product of the frequency division number and 48.67, that is, Q=f0/(48.67*N).