Research on mass production test of power grid communication chip

0 Introduction
IC testing is the process of testing integrated circuits or modules, and determining or evaluating the functions and performance of integrated circuit components by measuring the output response of the integrated circuit and comparing it with the expected output. It is an important means to verify design, monitor production, ensure quality, analyze failures, and guide application. According to the purpose of the test, the test can be divided into three categories: verification test, production test, and use test. This article mainly discusses production test. The basic purpose of production test is to identify defective chips and prevent them from flowing out of the manufacturing wafer and entering the next level of production process to save overall costs.
As the integration of integrated circuits continues to increase, the difficulty and complexity of testing are also increasing. At present, large-scale integrated circuit production testing has completely relied on automatic test equipment (ATE). The task of the test engineer is to formulate a test plan according to the product specification requirements of the device under test (DUT), and use the software and hardware resources of ATE to apply stimulus signals to the DUT, collect responses, and finally compare the output response with the expected signal or calculate the test results, and finally determine whether the chip meets the original design requirements to decide whether to ship or discard it. Chips that fail the test can be collected and returned to the manufacturer to analyze the failure reasons to improve the yield. According to the test plan, chip testing is divided into wafer testing (mid-test, also called CP testing) and packaging testing (finished test, also called FT testing). Among them, FT testing is also the last test of the finished chip to ensure the quality of the chip before it leaves the factory; while CP testing is mainly carried out in the early stage of chip mass production when the wafer yield is not high to reduce the cost of packaging failed chips. At the same time, the results of CP testing can also be fed back to the wafer manufacturer for process adjustment to improve the yield. The test program flow chart of its ATE is shown in Figure 1.

The three parts of the CP test program in the figure, Contact, Sean, and BIST, are consistent with the three parts in the FT test program. The difference is that the error handling (Fail deal) part is handled differently. In the CP test, the DUT is the entire wafer. The chips that fail the test can be marked by ink dots or machine recording positions. When the wafer is diced, the error chips are sorted and picked out, which is called BIN division. In the FT test, because the chips are already packaged, when the chip fails the test, the error chip is directly discarded or sorted by the robot (Handler). In order to make full use of ATE test resources, the FT test adopts a four-in-one test method; while the CP test is a transitional project in the early stage of mass production. In order to save the cost of probe card production, a single test method is adopted.
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1 Project Test Description
1.1 Contact Test
Use a diode between the tested pin and the ground to perform a connectivity test. Apply current to turn on the diode. When the connection is normal, the voltage value on the pin should be the diode voltage drop. As shown in Figure 2. The principle of the connectivity test between the pin and the power supply is the same.

In order to prevent the diode voltage deviation and the error in voltage measurement from causing unnecessary mass production losses, the judgment voltage values ​​in the actual test are: -1~0.1V for ground connectivity and 0.1~1V for power connectivity.
1.2 BIST, Scan Test
The test methods of BIST and Scan are basically the same, both of which input a test vector to the chip and then compare the output vector detection. The test vector (pattern) is converted from the waveform generation (WGL, Wave Generation Language) file obtained by the back-end simulation. BIST is a common functional test, which applies stimulus and judges the output. Although the Sean test is a structural test, for ATE, its test method is no different from the functional test, except that the Scan test can achieve a higher test coverage with fewer test vectors. The ATE functional test principle is shown in Figure 3.

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1.3 ADC test
According to the test plan, the analog waveform generator (HLFG) of ATE is used to generate a sinusoidal signal with a frequency of about 132 kHz as the analog input of the DUT. The digital code output of the chip is sampled by the DCAP module of ATE and stored in the memory. The test program then performs FFT analysis on the data stored in DCAP, calculates the SNR parameter, and determines whether the DUT passes the A/D test based on the SNR value.
The A/D test principle is shown in Figure 4.

When DCAP samples the digital output of the chip in the ADC test, a test vector file is required to control its sampling time, mainly to wait for the HLFG module to work stably, so as to avoid ADC test failure caused by incorrect input of the DUT.
1.4 D/A test method
During test development, a program is used to generate a digital sequence as the input vector for DAC test. According to the test plan, the digital sequence is a 132kHz signal sampled at 2.5MHz, with 8-bit quantization. ATE generates an 8-bit digital signal as the input of the DAC to be tested according to this vector file, and the analog output of the DUT is sampled by the analog waveform sampling module (HLFD) of the ATE. The test program performs FFT operation on the HLFD sampling result to obtain the SNR parameter, and determines whether the DUT passes the DAC test based on the SNR value. The D/A function test principle is shown in Figure 5.

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2 Problems and solutions in program debugging and use
2.1 Clock problem in ADC test
When debugging the ADC test program on site, it was found that the SNR was negative after the program was run. Using the System view of ATE, it was found that the DCAP had sampled the data and its spectrum was a single frequency point (sinusoidal signal).
Cause analysis: From the spectrum of the data in the DCAP, the ADC input signal is sine, and the sampling results in a sine sequence. At the same time, since the test program calculates the SNR based on the signal at 132 kHz, the possible result is a problem with the calculation program, or the sine signal generated by the HLFG module is not 132kHz.
After debugging again with an oscilloscope, it was found that the actual output frequency of the HLFG module was 205 kHz, while the output clock of the clock module was 3.9MHz, not the expected 2.5MHz. After reconfirming the clock module connection and program configuration, the clock returned to normal and the ADC test program passed the debugging.
2.2 Sampling problem in DAC test
At the beginning of the DAC program debugging, the ATE digital sequence was generated correctly and the DAC output a 132 kHz analog signal, but the HLFD module failed to successfully sample, and the sampling results were all 0.
By checking the manual and communicating with ADVANTEST engineers, we found two problems:
(1) ATE test programs are generally executed sequentially. In the program, the pattern is generated first and the HLFD is sampled later. Therefore, when the HLFD starts sampling, the digital sequence is no longer generated and the DAC will not have any output;
(2) The HLFD module requires a long sampling time because the data of the HLFD module is not directly sampled, but is calculated and restored after repeated sampling.
In response to these two problems, the test program was modified: the HLFD module was forced to run in parallel with the pattern sending in the program, and the pattern file was sent repeatedly 4 times to ensure that the HLFD module can complete the sampling.
After the modification, the HLFD module was sampled correctly and the DAC test program passed the debugging.
2.3 Clock module problem in the debugging of the four-simultaneous test program
During the four-simultaneous test, when the chip 1 test failed, the ADC and DAC tests of the remaining chips 2, 3, and 4 failed.
Cause analysis: If the chip 1 test fails and error handling is performed, ATE will give the robot (Handler) information to classify chip 1 as a faulty chip, and will not provide power or signal to chip 1 in subsequent test items. For ATE, the control signal line of the clock module is indistinguishable from the digital line of the chip. Therefore, after the test of chip 1 fails, ATE disconnects the control signal of the clock module, and the clock module works abnormally and causes ADC and DAC test failures.
There are two solutions to this problem: one is to test chips 2, 3, and 4 first in the program, and then test chip 1. The problem with this is that the test time of the four simultaneous tests will be doubled, which actually becomes a two-simultaneous test. The second method is to lead out four groups of clock analog control signals on the ATE, and perform OR with them. In this way, as long as there is a chip still being tested, this group of control signals can realize the correct configuration of the clock module, and there is no need to increase the test time. Only a part of the OR gate circuit needs to be added to the clock module.
2.4 DAC sampling problem during production test
After the program debugging was completed, it was officially put into use and has been working stably. When testing the third batch of chips, a large range of DAC test items failed. The phenomenon is that the SNR of most chips is slightly lower than the pass threshold, and the phenomenon is stable.
Cause analysis: Considering that the first two batches of chips (about 20,000 pieces) have been tested normally, and the chips that failed this test are all in a critical state, the initial guess is that the DUT may not be fully stable when the HLFD is sampled. By analyzing the DAC test program, HLFD starts sampling immediately after the pattern occurs. The stabilization time of this batch of chips may be different from that of the previous two batches, which leads to the failure of the DAC test. A 10 ms delay is added before the HLFD module is sampled to ensure that the DUT works stably. The test is retested and the fault problem is solved.

3 Test cost compression
The cost factor affects the development of the test from beginning to end. When formulating the test plan, the reduction of test cost is taken into account. When the CP test yield is very high, so that the CP test cost is greater than the packaging cost of the failed chip, the CP test can be considered to be cancelled. However, in the early stage of mass production, the CP test also serves the purpose of providing information feedback to the wafer factory. From the feedback of chip applications, it is found that USER_ADC and USER_DAC are almost never used. Therefore, after communication with the system integrator, the test of USER_ADC and USER_DAC was cancelled in the FT test to reduce the test cost.
Another way to further reduce the test cost is to classify the test failure results of SCAN. If some parts of the pattern have never failed, they can be considered to be cancelled without affecting the test results.

4 Conclusions
With the development of integrated circuits, the reduction of chip feature size and the increase of complexity have had a huge impact on test methodology. At the same time, the trend of high speed and mixed digital and analog has brought cost pressure to the demand for high-performance ATE. This paper first discusses the common test methods of mixed digital and analog chips, and then implements the test development and debugging based on Advantest T6575, and finally ensures the smooth mass production of the power grid communication chip. This test procedure has actually tested more than one million chips shipped from the Fujitsu packaging and testing plant in Nantong, ensuring the chip quality and meeting the expected design requirements.