Jitter Analysis and Measurement of Reference Clocks in High-Speed ​​Interconnect Links

Introduction to high-speed interconnection links
Any communication link consists of three parts: transmitter (TX), medium (channel), and receiver (RX). For high-speed serial interconnection links, these three parts are also included. Figure 1 below shows the structure of a typical high-speed interconnection link. The transmitter includes: parallel-to-serial conversion, encoding (such as 8b10b encoding), transmission signal optimization (such as pre-emphasis), transmission drive and other functions. The receiver includes: clock recovery, data recovery, reception signal optimization (such as equalization), serial-to-parallel conversion, decoding and other functions. The transmission channel is composed of printed circuit board routing, vias, connectors, card gold fingers, cables, optical fibers, etc.

From the perspective of the entire link, the jitter of the transmitter reference clock is introduced into the entire link during the serial-to-parallel conversion, affecting the jitter of the data sent by the TX end, and the receiver needs to recover the clock from these data for subsequent processing. It can be seen that the performance of the transmitter reference clock plays a critical role in the performance of the entire link. This article analyzes and discusses clock jitter testing from the perspectives of clock jitter related concepts, test examples, test precautions, and test difficulties.

Figure 1: Schematic diagram of the structure of a serial interconnect link

Definition of three types of clock jitter, peak-to-peak value and effective value
Clock jitter is usually divided into three types: time interval error (TIE), period jitter and cycle to cycle jitter.

TIE, also known as phase jitter, is the offset between the edge of a signal and the ideal time position when the signal is level-converted. The ideal time position can be recovered from the clock to be tested, or from other reference clocks. As shown in Figure 2, the schematic diagram of TIE jitter, I1, I2, I3, In-1, In are the deviations from the first to the nth rising edge of the clock and the ideal time position. Mathematical statistics are performed on I1, I2 to In, and the maximum and minimum values ​​are found in all samples. Subtracting the two can obtain the peak-to-peak value of TIE jitter, that is:

Assuming N is the total number of samples measured, the average value of jitter can be expressed as:

The effective value (RMS value) of jitter is 1 Sigma value of all samples, that is:

Period jitter is the result of statistics and measurement of the change of clock period in multiple cycles. P1, P2, Pn-1, and Pn shown in Figure 3 are the period values ​​of the clock in multiple cycles. These values ​​are mathematically counted. Similarly, the peak-to-peak value and effective value calculation method of TIE jitter is the same. The maximum value from P1 to Pn is subtracted from the minimum value to obtain the peak-to-peak value of the period jitter. A Sigma operation is performed on P1 to Pn to obtain the RMS value of the period jitter. [page]

Cycle to cycle jitter is the result of statistics and measurement of the cycle difference between adjacent clock cycles. As shown in Figure 4, the next clock cycle minus the previous clock cycle is used as the statistical sample, C1=P2-P1, C2=P3-P2, Cn-1 = Pn - Pn-1, C1 to Cn-1 are mathematically counted, and similarly, the peak-to-peak value and RMS value of cycle to cycle jitter can be calculated.

Among the three common clock jitters mentioned above, for serial buses, TIE jitter is usually measured, such as the reference clock at the TX end of a high-speed transceiver. For parallel circuits, the period jitter and adjacent period jitter of the clock are usually measured, such as DDR SDRAM, FSB on a PC motherboard, etc.

The red curve in Figure 2, Figure 3, and Figure 4 has time on the horizontal axis and jitter values ​​of the corresponding period on the vertical axis. This curve reflects the trend of jitter changes over time and is called jitter track. The jitter values ​​of each period (such as I1, I2, ...In of TIE jitter) are statistically histogrammed to obtain a jitter histogram. The jitter track is subjected to fast Fourier transform (FFT) calculation to obtain a jitter spectrum.

Jitter tracking is the manifestation of jitter in the time domain, jitter spectrum is the manifestation of jitter in the frequency domain, and jitter histogram is the manifestation of jitter in the statistical domain. Various test instruments and analysis software measure and analyze jitter in these three domains.

Figure 5 below is a schematic diagram of analyzing the TIE jitter of a 100MHz clock in the time domain, frequency domain, and statistical domain. F2 in the upper left corner is a 100MHz clock, and P1 is the TIE parameter measurement of the clock; F3 in the upper right corner is the histogram of TIE jitter. The histogram is not a Gaussian distribution, which shows that the clock has inherent jitter. [page]

Figure 5: Analysis of clock jitter in the time domain, spectrum, and statistical domains

F4 in the lower left corner is the TIE track (i.e. the trend of TIE jitter changing over time). The periodic change trend can be seen from the TIE track; F5 in the lower right corner is the FFT operation of F4, i.e. the spectrum of jitter. The peak frequency of the spectrum is 515kHz, indicating that the main source of the periodic jitter (PJ) of the clock is 515kHz. After finding the frequency point, you can find the chip and PCB trace on the circuit board whose main frequency or harmonic is the frequency for further debugging and analysis. [page]

Decomposition of clock jitter
The peak-to-peak value and RMS value of clock jitter only reflect the statistical value of jitter, and do not analyze the source of jitter. For clock jitter decomposition, the industry usually decomposes jitter into: total jitter (TJ), deterministic jitter (DJ), random jitter (RJ), periodic jitter (PJ), duty cycle distortion (DCD), etc. The following Figure 6 shows the relationship between various jitters.

TJ and its various components are all for TIE. As mentioned above, TIE reflects the deviation between the measured clock and the ideal clock. The peak-to-peak value of TIE jitter increases with the increase in the number of test samples (caused by random jitter factors). TJ is related to the bit error rate. The bit error rate is usually 10E-12, that is, the TJ usually referred to is the peak-to-peak value of TIE jitter of 10 to the 12th power samples. TJ includes RJ and DJ, and DJ includes PJ, DCD, and BUJ (other bounded data-independent jitter). For clocks that are synchronized and timed by a single edge, DCD is not counted as jitter (of course, most clocks only use their rising edge).

RJ will increase with the increase of sample number, and its histogram satisfies Gaussian distribution, which is usually expressed by 1 Sigma or RMS value after statistics. The RJ obtained in jitter test instrument is usually RMS value. Random jitter comes from thermal noise, shot noise and flick noise, which is related to the electron and hole characteristics of electronic devices and semiconductor devices. For example, PLL of ECL process has smaller random jitter than PLL of TTL and CMOS process.

DJ is a bounded, deterministic jitter, which comes from switching power supply noise, crosstalk, electromagnetic interference, etc. It is related to the circuit design and can be improved by optimizing the design, such as choosing a suitable power supply filtering solution and reasonable PCB layout and wiring.

In the jitter spectrum, RJ is the base part of the spectrum, while DJ is the peak part of the jitter spectrum. Many test instruments decompose jitter from the jitter spectrum.

Notes on clock jitter testing
In clock jitter testing, there are the following key points:

Select the appropriate bandwidth: In order to accurately measure the edge of the clock, the bandwidth of the oscilloscope is usually more than 5 times the clock frequency. For some clocks with very fast edges, the instrument bandwidth may even be greater than 10 times the clock frequency.
Select the appropriate test point: Since the clock link may use various termination strategies or star topology structures, it may not be very meaningful to detect the clock at the transmitting end. Usually, detection and analysis are performed near the receiving end of the clock link.
Ensure that the ground wire is as short as possible: When the ground wire of the probe is long, the parasitic inductance introduced may cause the measured waveform to be distorted, and the signal loop formed by the long ground wire is also more susceptible to electromagnetic interference.
The signal amplitude should fill the entire screen as much as possible: The ADC of the oscilloscope has only 8 bits of resolution. The signal amplitude must fill the entire screen of the oscilloscope as much as possible to ensure sufficient test accuracy.
Fix to the appropriate sampling rate: Use the appropriate sampling rate to ensure that enough sampling points are collected at the edge of the clock.
Capture enough clock cycles: For clocks with lower frequency PJ, it is necessary to capture a long enough time to find the jitter source of the clock.
Difficulties in clock jitter evaluation
In the current test and analysis of the clock of communication equipment, there are problems: the definition of the meaning of clock jitter indicators by chip, equipment, and test instrument manufacturers is inconsistent. For example, some chip manufacturers directly give the pk-pk value of jitter without specifying the jitter requirement. The name given by the chip manufacturer is consistent with the name of the test instrument manufacturer, but the actual meaning of the description is inconsistent.

Some chip manufacturers do not have strict requirements for clock jitter indicators; some chip manufacturers give arbitrary clock jitter indicators, and there is no corresponding basis for the indicators. The reason is that the operating speed and clock frequency of electronic products have been increasing in the past decade, and the knowledge of jitter has been continuously improved and theorized. However, the definition of jitter in the documents of some chip manufacturers is not standardized, which brings certain difficulties to the evaluation of clock performance. These require their own accumulation to conduct evaluation.

Conclusion
High-speed links are an important part of all electronic devices in the future, and their design, performance analysis and evaluation are all hot topics. This article only discusses the basic concepts and tests of clock jitter, and the separation technology of each component of jitter, the performance of clock jitter in the time domain and frequency domain and their relationship, the source of jitter, jitter improvement, and the impact of jitter on the system in different application scenarios are all contents that circuit design and test engineers need to study in depth.

Reference
"jitter slides"----LeCroy
"Jitter, Noise, and Signal Integrity at High-Speed"---Mike Peng Li