Improving circuit design procedures to improve testability

As miniaturization continues, component and wiring technology has also made great progress, such as highly integrated micro ICs in BGA housings and insulation spacing between conductors down to 0.5 mm, are just two examples. The way in which electronic components are wired has an increasing influence on whether the tests in the subsequent production process can be carried out well. Here are some important rules and practical tips.

By following certain rules (DFT-Design for Testability), the preparation and implementation costs of production tests can be greatly reduced. These rules have been developed over the years and, of course, they must be expanded and adapted accordingly if new production and component technologies are adopted. With the increasingly small dimensions of electronic products, two particularly striking problems have emerged: one is that there are fewer and fewer accessible circuit nodes and the other is that the application of methods such as in-circuit testing is limited. To solve these problems, corresponding measures can be taken in the circuit layout, new test methods and innovative adapter solutions. Solving the second problem also involves making the test system, which was originally used as a separate process, take on additional tasks. These tasks include programming memory components or implementing integrated component self-test (Built-in Self Test, BIST) through the test system. In general, transferring these steps to the test system
still creates more added value. In order to successfully implement these measures, corresponding considerations must be made during the product research and development stage.

What is testability?

Testability can be understood as: the test engineer can use the simplest method possible to test the characteristics of a certain component to see if it meets the expected function. Simply put:

l How simple is the method for testing whether the product meets the technical specifications?

l How fast can the test program be compiled?

l How comprehensive is the product failure?

l How simple is the method for accessing the test point?

In order to achieve good testability, mechanical and electrical design procedures must be considered. Of course, to achieve the best testability, it is necessary to pay a certain price, but it has a series of benefits for the entire process and is therefore an important prerequisite for the successful production of the product.

Why develop test-friendly technology?

In the past, if a product could not be tested at the previous test point, the problem was simply pushed to the next test point. If a product defect cannot be found during production testing, the identification and diagnosis of this defect will simply be pushed to functional and system testing.

On the contrary, people today try to find defects as early as possible. The benefit is not only low cost, but more importantly, today's products are very complex and some manufacturing defects may not be detected at all during functional testing. For example, some components that need to be pre-installed with software or programmed have such problems. (For example, flash memory or ISPs: In-System Programmable Devices). The programming of these components must be planned in the development stage, and the test system must also master this programming.

Test-friendly circuit design costs some money, however, circuit design that is difficult to test costs more. Testing itself has a cost, and the cost of testing increases with the number of test levels; from in-circuit testing to functional testing and system testing, the cost of testing is increasing. If one of the tests is skipped, the cost will be even greater. The general rule is that the cost of each additional level of testing increases by a factor of 10. Through test-friendly circuit design, faults can be found early, so that the cost of test-friendly circuit design can be quickly recovered.

How documentation affects testability

Only by making full use of the complete data of the component development can it be possible to compile a test program that can fully detect faults. In many cases, close cooperation between the development department and the test department is necessary. Documentation has an indisputable influence on the test engineer's understanding of the component function and the development of the test strategy.

In order to circumvent the problems caused by the lack of documentation and the lack of understanding of the component function, the test system manufacturer can rely on software tools that automatically generate test patterns according to the random principle, or rely on non-vector methods, which can only be regarded as a stopgap solution.

The complete documentation before testing includes the parts list, the circuit design data (mainly CAD data) and the detailed information about the function of the component (such as the data sheet). Only with all the information is it possible to compile test vectors, define the component failure mode or make certain pre-adjustments.

Certain mechanical data are also important, such as those required to check whether the components are well soldered and positioned. Finally, for programmable components such as flash memory, PLD, FPGA, etc., if they are not programmed at the final installation, but should be programmed on the test system, the respective programming data must also be known. The programming data of flash components should be complete. If a flash chip contains 16Mbits of data, 16Mbits should be available to prevent misunderstandings and avoid address conflicts. This may happen, for example, if a 4Mbit memory is used to provide only 300Kbits of data to a component. Of course, the data should be prepared in a popular standard format, such as Intel's Hex or Motorola's S-record structure. Most test systems can interpret these formats as long as they can program flash or ISP components. Many of the information mentioned above are also necessary for component manufacturing. Of course, a clear distinction should be made between manufacturability and testability, as these are completely different concepts and thus constitute different prerequisites.

Mechanical contact conditions for good testability

If the basic rules of mechanical aspects are not taken into account, even circuits with very good electrical testability may be difficult to test. Many factors can limit electrical testability. If the test points are not enough or too small, it will be difficult for the probe bed adapter to contact every node of the circuit. If the test point position and size errors are too large, poor test repeatability will occur. When using a probe bed adapter, a series of recommendations on the size and positioning of the locking holes and test points should be paid attention to.

Electrical prerequisites for optimal testability

The electrical prerequisites are as important for good testability as the mechanical contact conditions. Neither is possible without the other. A gate circuit cannot be tested because the enable input cannot be contacted via the test point or because the enable input is located inside the package and cannot be contacted from the outside. In principle, both situations are equally bad and make testing impossible. When designing the circuit, it should be noted that all components to be tested by in-circuit testing methods should have some mechanism to electrically isolate the components. This mechanism can be achieved with the help of an inhibit input, which can control the output of the component to a static high-ohmic state.

Although almost all test systems can backdrive the state of a node to any state, it is best to have an inhibit input for the node involved, which first brings the node to a high-ohmic state and then "gently" applies the corresponding level.

Similarly, the clock generator is always disconnected directly from the oscillator via the enable pin, the gate circuit or the plug-in bridge. The enable input is never connected directly to the circuit, but via a 100-ohm resistor. Each component should have its own enable, reset or control pin. It must be avoided that the enable inputs of many components share a common resistor connected to the circuit. This rule also applies to ASIC components, which should also have a pin through which the output can be brought to a high-ohmic state. If the component can be reset when the operating voltage is connected, this is also very helpful for the reset to be triggered by the tester. In this case, the component can simply be placed in a specified state before testing.

Unused component pins should also be accessible, because undetected shorts in these locations can also cause component failure. In addition, unused gates are often used in design improvements at a later time, and they may be reconnected to the circuit. So it is also important that they should be tested from the beginning to ensure that they are reliable workpieces.

Improved Testability

Recommendations for improved testability when using a probe bed adapter

Hold-down holesl

Diagonal configurationl

Positioning accuracy ±0.05mm (±2mil)

l Diameter accuracy ±0.076/-0mm (+3/-0mil)

l Positioning accuracy ±0.05mm (±2mil) relative to the test point

l At least 3mm away from the edge of the component

l No through-contact

Test pointsl Square

as far as possiblel

Test point diameter at least 0.88mm (35mil)

l Test point size accuracy ±0.076mm (±3mil)

l Test point spacing accuracy ±0.076mm (±3mil)

l Test point spacing 2.5mm as far as possible

l Tinned, solderable ends

l At least 3mm from the edge of the component

l All test points should be on the back of the board as far as possiblel

Test points should be evenly distributed on the boardl

At least one test point per node (100% of channels) l

Test points for spare or unused gatesl

Multiple external test points of the power supply are distributed in different positions

Component marking

l Marking text in the same direction

l Model, version, serial number and barcode are clearly marked

l Component name should be clearly visible and marked as close to the component as possible

About flash memory and other programmable components

Flash memory programming time can sometimes be very long (up to 1 minute for large memories or memory groups). Therefore, it is not allowed to reverse drive other components at this time, otherwise the flash memory may be damaged. To avoid this, all components connected to the control lines of the address bus must be placed in a high-ohmic state. Similarly, the data bus must also be able to be placed in an isolated state to ensure that the flash memory is unloaded and can be programmed in the next step.

There are some requirements for in-system programmable components (ISP), such as products from companies such as Altera, XilinX and Lattuce, and some other special requirements. In addition to the mechanical and electrical prerequisites for testability, it is also necessary to ensure the possibility of programming and confirming data. For Altera and Xilinx components, the serial vector format (Serial Vector Format SVF) is used, which has almost become an industrial standard in recent years. Many test systems can program such components and use the input data in a serial vector format (SVF) for the test signal generator. These components are programmed via the boundary scan key (Boundary-Scan-Kette JTAG), which also programs the serial data format. When compiling the programming data, it is important to consider the entire chain of components in the circuit and not to restore the data to only the component to be programmed. When

programming, the automatic test signal generator considers the entire component chain and connects the other components into the bypass model. In contrast, Lattice requires data in JEDEC format and programming in parallel via the usual inputs and outputs. After programming, the data is also used to check the function of the component. The data provided by the development department should be as easy as possible to use directly in the test system or can be applied by simple conversion.

What to pay attention to about boundary scan (JTAG)

Components composed of a fine grid based on complex components provide the test engineer with only a few accessible test points. At this time, it is still possible to improve testability. Boundary scan and integrated self-test technology can be used to shorten test completion time and improve test results.

For the development engineer and test engineer, a test strategy based on boundary scan and integrated self-test technology will definitely increase costs. The development engineer must use the boundary scan components (IEEE-1149.1-standard) in the circuit and try to make the corresponding specific test pins accessible (such as test data input-TDI, test data output-TDO, test clock-TCK and test mode selection-TMS as well as ggf. test reset). The test engineer creates a boundary scan model for the component (BSDL-Boundary Scan Description Language). At this time, he must know which boundary scan functions and instructions the component supports. Boundary scan testing can diagnose short circuits and open circuits down to the pin level. In addition, if the development engineer has specified it, the automatic test of the component can be triggered by the boundary scan instruction "RunBIST". Especially when there are many ASICs and other complex components in the circuit, for which there is no conventional test model,
the cost of developing the test model can be greatly reduced by using boundary scan components.

The degree of time and cost reduction is different for each component. For a circuit with IC, if 100% discovery is required, about 400,000 test vectors are required. By using boundary scan, the number of test vectors can be reduced to hundreds at the same fault discovery rate. Therefore, the boundary scan method has special advantages under the condition that there is no test model or the nodes contacting the circuit are limited. Whether to use boundary scan depends on the cost increase in the development and manufacturing process. Boundary scan must be weighed with the time required to discover faults, test time, time to enter the market, and adapter costs, and save as much as possible. In many cases, a mixed solution of traditional online test methods and boundary scan methods is the best solution.