An Effective Method to Improve Test Coverage of DFT Design

With the rapid development of modern large-scale integrated circuit manufacturing processes, design engineers must face the physical defects that may occur in the chip manufacturing process. Today's popular design for testability (DFT: Design For Testability) came into being and plays an increasingly important role in ensuring the yield of chips.

In DFT design, test coverage and test efficiency are the most important indicators. On the one hand, the ideal design goal is of course to hope that the test can cover the logic of the entire chip, although the ideal value of 100% is not easy to achieve; on the other hand, test efficiency is also very important. Design engineers always hope to use the least test vectors to achieve the expected test coverage to reduce the test cost of the chip.

Of course, DFT design must ensure normal logical functions as a prerequisite. Unfortunately, functional design always ignores some potential problems, resulting in the final test coverage is often unsatisfactory. In this case, some logic in the design cannot be observed or controlled anyway, so even if the number of test vectors increases significantly, the results cannot be improved much.

In actual DFT design, there are two situations that greatly damage the test coverage: one is the shaded part of the input-output of digital logic-analog logic (including memory), and the other is the unbound input-output pads in a specific multi-chip package. The common point between the two is that part of the logic is uncontrollable or unobservable in the test mode.

Design Background

The design target discussed in this paper is a digital audio signal processing chip from STMicroelectronics, which requires scan chain testing of digital functional logic with a coverage rate of more than 98%. There are some analog modules in its functional logic, such as phase-locked loops, analog-to-digital converters, and some memory cells. More importantly, the chip needs to be packaged in a separate form based on different application system needs, and multiple chips need to share the same package. In this way, in some multi-chip packages, some pads are not brought out or grounded. The original intention of the test design is to generate a set of test vectors applicable to all package shapes, which requires considering the pin resources available under the most stringent package.

DFT design has two basic principles: controllability and observability, that is, DFT design requires all input logic to be controllable and output logic to be testable. Obviously, considering the limited resources of the analog module interface and package form in this design, uncontrollable logic and unobservable logic pose a great challenge to the target test coverage rate of not less than 98%.

As shown in Figure 1, in a certain chip packaging situation, except for the signals test_si and test_so, the other pads are not tied out (grounded or suspended), which makes the signals port_A, port_B, port_C and port_D uncontrollable, and the signals port_Z1, port_Z2 and port_Z3 unobservable (suspended). As a result, many related logics cannot participate in DFT testing normally, and the test coverage is greatly damaged.

Figure 1: Uncontrollable and untestable test logic caused by encapsulation

The controllability and observability of DFT design are achieved through the original pins. In fact, it is impossible for the functional design to reserve enough pins specifically for DFT. As shown in Figure 2, due to the existence of the PLL module, the test results obtained on the signals net_1, net_2 and net_3 cannot be directly observed (untestable), and the corresponding test coverage of combinational logic 1 is reduced; at the same time, due to the existence of the PLL module, the signals net_4, net_5 and net_6 cannot be directly assigned (uncontrollable), resulting in part of the logic of combinational logic 2 cannot participate in the DFT test normally, and the corresponding test coverage is greatly damaged. In general, the test coverage of the chip is reduced.

Figure 2: Test logic is uncontrollable and untestable due to simulation module

Solution

For the above situation in the design, the previously uncontrollable and untestable logic changes can be reflected on the scan chain by adding test points appropriately, making them indirectly controllable and testable, in order to improve the test coverage and test efficiency of the entire chip.

For the uncontrollable and untestable unbound (grounded or floating) pins in some packages shown in Figure 1, Figure 3 provides the corresponding customized solution.

Figure 3 Adding control points and observation points to improve test coverage (some package pins are not tied out)

For the input pins, add a register with a selection terminal. When the control selection signal is "0", the circuit is in normal working state, and the functional logic receives the normal input value from the input terminal. When the selection control is "1", the circuit is in the test state. During the shift process, these points are preset with corresponding values ​​by the test chain; during the capture process, they are grounded to prevent the propagation of indeterminate states in the design.

At the output pins, add a small number of XOR gates and selection devices. When the control selection signal is "0", the circuit is in normal working state, and the output pins output functional signals normally. When the selection control is "1", the circuit is in the test state, and the XOR gate is used to lead out the changes of the pins that cannot be tied out, which is equivalent to these pins can also be observed.

For the digital-analog interface shown in Figure 2, some analog module input signals are given through combinational logic, but there is no logic to bring out the signal effects of these "end points" for observation during testing, so these points are unobservable. This is inconsistent with the observability requirements of DFT design (direct output of pins is required), which may cause damage to test coverage. At the same time, some analog module output signals control the corresponding combinational logic, but in testing, these points are "floating" (uncontrollable). This is inconsistent with the controllable requirements of DFT design (direct input of pins is required), resulting in reduced test coverage. Figure 4 shows a customized solution similar to the former, which is essentially to connect these uncontrollable and untestable points to the test chain, making these logics indirectly observable or controllable to improve test results.

Figure 4 Adding control points and observation points to improve test coverage (digital-analog interface case)

As shown in the figure, add a small number of XOR gates and selection devices at the input signal of the analog module, and connect them to the scan chain. When the control selection signal is "0", the circuit is in normal working state, and the input pins of the analog module receive functional signals normally. When the selection control is "1", the circuit is in the test state, and the changes of the pins that cannot be observed are led out by XOR gates or other devices, which is equivalent to these pins being indirectly observed.

As shown in the figure, a register with a selection terminal is added at the output signal of the analog module. When the control selection signal is "0", the circuit is in normal working state, and the analog module signal is normally output to the subsequent functional logic. When the selection control is "1", the circuit is in the test state: during the shift process, these points are preset with corresponding values ​​by the test chain; during the capture process, they are grounded to prevent the propagation of indeterminate states in the design.

For other analog modules such as ADC, memory, etc., similar methods can be used to improve the test coverage and test efficiency of the entire chip and achieve the target test effect.

Conclusion

In the DFT design of the actual project mentioned above, the functional logic part contains more than 10,000 registers. In order to improve the test coverage, only 12 registers and a small part of the combinational logic are added as test points, and the test coverage can be increased from the original 95% to 98.3%. From this point of view, this method is very efficient. And according to the actual needs of the project, more points can be added to achieve a higher coverage. In theory, the test coverage can be close to 100%.

It is recommended that this test structure be considered during RTL functional design. In this way, design engineers can understand each other's design requirements, the functional test structure is clear, and a lot of trouble can be saved during the DFT design process. If such problems are found after RTL is completed, some DFT tools also provide user-defined test point insertion, but it should be noted that the test control signal selection must match the required test mode, otherwise the corresponding test expectations cannot be met. The key to this method is to understand where to add test points more effectively.