Design of high-speed variable-period pulse generator based on FPGA

1 Introduction

Pulse output circuit modules that require changing the pulse cycle and the number of output pulses are used in many industrial fields. It is convenient and feasible to use digital devices to design a pulse generation module with adjustable cycle and output number. In order to make it have the advantages of high speed and flexibility, this paper uses Atelra's programmable chip FPGA to design a pulse generator with variable cycle and output number. After board-level debugging, good operation results are obtained.

2 Overall design ideas

The pulse cycle is composed of the high level duration and the low level duration. In order to change the cycle, two counters are used to control the high level duration and the low level duration respectively. The counter uses an N-bit subtraction counter that can load the initial value in parallel. Setting: When the required high level time is loaded into the first subtractor with the initial value, the subtractor starts to count down, and automatically stops when the count reaches zero, and starts the second counter that records the low level duration. When the second subtraction counter also counts to zero, the counter stops automatically.

In this way, the output of a pulse is completed, and the cycle control of this pulse can be effectively set in the initial value of the counter. To achieve the purpose of adjustable pulse cycle. In order to control the output of the number of pulses, a quantity control counter is designed on the pulse output channel to count the number of pulses. When the required number of pulses is reached, the output is completed and a done signal is given as a sign that the module is finished. The design block diagram of the encapsulated pulse generator is shown in Figure 1.

Pin signal description:

start signal: start signal.

reset, signal: system reset signal.

clock signal: system clock signal.

high signal: initial value of high level duration.

low signal: initial value of low level duration.

num signal: initial value of number control register.

output signal: pulse output signal. Low during initialization.

done signal: sign signal of pulse output completion.

3 High and low level timer design

3.1 Design method

In order to generate the high level required for the time, a preset subtraction counter can be used to achieve the purpose. The counter design is divided into two parts. One part is a preset self-controlled subtraction counter: the other part is the detection system after the subtraction counter is completed. After the counter is detected to be completed, a pulse with a clock cycle width is output as the completion signal of the counter, and it can be used as the start signal of the next counter. The principle block diagram is shown in Figure 2.

3.2 Working Principle

The design of the low-level timer is exactly the same as that of the high-level timer.

3.3 Timing Simulation

The two output signals of this module are simulated on the QuartusⅡ4.1 development platform, and the timing simulation is shown in Figure 3.

As can be seen from the figure, the done signal outputs a clock cycle width after the pulse signal is output. Adding this completion signal done to the start signal of a similar subtraction counter at the next level will start the work of the next level counter. If the completion signal done of the next level is added to the start signal of this level, the generation of a pulse will be restarted. In this way, it will automatically cycle to achieve the purpose of continuously outputting a certain period of pulses.
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4 Design of quantity control counter

4.1 Design method

The design of quantity control counter is similar to that of high and low level counter. The difference is that the clock input of subtraction counter is connected to the output signal of pulse. When the required number of output pulses is reached, a gate signal door is output. The two D flip-flops at the back are still used to capture the trailing edge of gate signal door. Once the output number is reached, done signal immediately outputs a pulse with the width of a clock cycle as a flag. The specific design block diagram is shown in Figure 4.

4.2 Timing Simulation

Soft simulation is performed on the QuartusⅡ4.1 development platform. The start signal of each pulse generated by the pulse generator is used as the input signal of the quantity controller. The simulation results are shown in Figure 5.

After each output task is completed, the overall module outputs an OV signal to mark the end of the batch task. The OV signal can be loaded onto the total reset signal again, that is, the output of the batch can be reset to the output of the next batch task. The door signal in Figure 5 has a very narrow burr, which is caused by the asynchronous flipping of the internal counter. Adding a synchronization circuit can eliminate it, but it will affect the operating frequency of the circuit. Since the burr is very narrow, it has no effect on the operation of the entire circuit. Therefore, this module is not processed in the design.

5 Internal signal connection and working mode

According to the functions and logical relationships of each module, the entire periodic pulse generator can be built by a high-level timer, a low-level timer and a quantity control counter. Its internal circuit is connected as shown in Figure 6.

First, a reset signal with a clock cycle width is given at the rising edge of the clock signal to reset the triggers and various output signals of the entire circuit. When a start signal start is detected at the rising edge of the clock, the high level starts timing, and the timing length is equal to the product of the high value and the clock cycle. When the timing is reached, the high-level timer stops working, and the high-level timer outputs a completion signal, which is connected to the start signal pin of the low-level timer to start the low-level timer. When the low-level timer is completed, the low-level timer stops working and outputs a completion signal, which is connected to the start signal pin of the high-level timer through the OR gate, and the high-level timer is started again to start the output of the second pulse high level. Since the completion signal of the low-level timer is also connected to the start pin of the quantity control counter. Therefore, at the same time, the quantity control counter starts to monitor the quantity of its input pulse s_input. When the number of pulse outputs does not reach the predetermined number (the initial value in the quantity control counter), the gate signal door always outputs "high" to allow the pulse to pass. Once the number of pulse outputs reaches the predetermined number, the gate signal door output becomes "low", the output channel is closed, and a task completion signal done is output. Done is connected to the global reset signal reset through an OR gate, so the system can be reset to its original state after completion to wait for the next start signal.

The overall timing simulation of the periodic pulse generator module is shown in Figure 7.

Figure 7 simulates the output of two pulses. The first pulse outputs two pulses and the second pulse outputs one pulse. When both pulses are output, the system returns to the initial state. When the start signal gives a start pulse again, the task will be executed again.

6 Conclusion

From the simulation results, it can be seen that the design given in this paper can fully meet the design requirements. Since the operating speed of FPGA can reach the order of 100 MHz at most, the output pulse adjustment step and minimum width can reach the order of ns. On this basis, the author designed a timing circuit with multiple adjustable pulse periods and applied it in the nuclear physics experiment of cluster particles. Satisfactory results were received.

First, the external reset signal reset gives a pulse with a clock cycle width to reset the internal signals and triggers. Then, at the next valid clock moment, the external start signal gives a pulse with a clock cycle width to start the counter. In the design, when the start signal is valid (designed to be high valid), the external data high is loaded to Q. When Q is not zero, the output signal pulse will jump to a high level. When Q decreases to zero, the pulse signal jumps back to a low level. The trailing edge of this pulse signal will be captured by the detection unit composed of two D flip-flops, and a pulse with a clock cycle width will be generated after the falling edge of the pulse signal, which is defined as the done signal, indicating that the signal has completed the output.