High-speed random number generator simplifies eye-diagram testing

One of the effective methods to evaluate the quality of digital communication links is the eye diagram, which gives a window for each bit (the Nth bit, between the N-1 random number and the N+1 random number). Communication system engineers generally use traditional test instruments to measure and analyze the bit error rate of the channel. But most professional engineers do not do this. For them, the circuit in Figure 1 provides an alternative method - the stimulus comes from a digital signal source.

Figure 1 High-quality random number generator for eye diagram testing

Resistors R1 and R2 form a VCC/2 bias and are bypassed to ground by C1. A 1MW resistor (R3) is used as a broadband, small-signal noise source. Op amps U1A and U1B provide a 5x AC voltage gain, but at low frequencies, the gain drops to 1 due to C2 and C4. The amplified noise output of U1B further drives comparator U2, which outputs a digital signal suitable as the input to the U3A and U3BD class flip-flops.

The comparator output is fed back to its inverting input through a low-pass filter, forming an output signal with a duty cycle close to 50%. In this way, a random data stream synchronized with the circuit input clock can be obtained at the output of U3A. Unfortunately, the output signal of the comparator often affects the setup and hold time of U3A, causing large jitter. This problem can be solved by passing the data stream signal through a D flip-flop (U3B) synchronized with the clock. The operating rate of this circuit can reach 62.5Mbps (see the eye diagram shown in Figure 2). When working at 20Mbps, the jitter is less than 200PS (peak-to-peak value), which is suitable for communication protocols such as RS-422, RS-484, CAN, USB, RS-232, PROFIBUS, etc.

Figure 2: 20Mbps eye diagram output in Figure 1, up to 62.5Mbps

The operational amplifier, comparator, and D flip-flop should be selected according to the specific application. The bandwidth of the operational amplifiers U1A and U1B should reach the highest output signal frequency expected by the user (in this case, the MAX1428 gain-bandwidth product reaches 25MHz). The stable gain of the operational amplifier is greater than or equal to 10 times, but for current applications, stability is no longer a major concern. In order to obtain a reasonable level of random numbers, the transmission delay of the comparator should be able to reach the level of the expected minimum bit rate period (too much transmission delay may cause a bit between N-1, N, and N+1 to be lost). MAX961 is a good choice, with a transmission delay of only 4.5ns. The flip-flop needs to provide a fast rise time and clean edges, as well as minimal or no overshoot. The 74HVC74 can be selected to maintain the same operating voltage range as the operational amplifier and comparator: 2.7V-5.5V. The operating voltage range of the 74HVC74 can reach 2V-5.5V, and the minimum switching frequency can reach 80MHz (3V power supply).

The circuit can be powered by a 2.7V-5.5V power supply. For best results, the clock swing should be able to reach the full swing range from the power supply to ground and be terminated with a 50W load. Connect the output random data stream to the device under test (DUT) with a short cable. Do not terminate the data stream signal because the trigger cannot drive a 50W load. Since the trigger divides the clock signal by 2, the expected output bit rate must be used as the clock frequency (for example, to get a rate of 10Mbps, the clock frequency should be set to 10MHz). Connect the output of the device under test to an oscilloscope with sufficient bandwidth to meet the test requirements, the persistence should be set to infinite, and synchronized with a clock source.