[Solved] GD32F307RCT6, soft reset cannot be completed during Ethernet initialization (SWR bit is always 1)

lerm

[Solved] GD32F307RCT6, soft reset cannot be completed during Ethernet initialization (SWR bit is always 1) [Copy link]

 

I was recently debugging the Ethernet function module of the GD32F307RCT6 microcontroller and encountered the following problems that could not be solved:

1. As shown in Figure 1 and Figure 2, there is a step in the Ethernet initialization process to wait until the SWR bit of the ENET_DMA_BCTL register is automatically cleared by the hardware. I used the official routine in the SDK package: \GD32F30x_Demo_Suites_V2.1.0\GD32307C_EVAL_Demo_Suites\Projects\22_ENET\Projects\Raw_tcpudp, but after the code runs, the SWR bit cannot be cleared (as shown in Figure 3 below), and then after the timeout return, it will be stuck in a while loop and cannot execute further.

2. In Figure 3, you can use ENET_DMA_BCTL &= ~ENET_DMA_BCTL_SWR; to manually clear, but although the Ethernet initialization process can be completed, subsequent communication with the PHY module will not be successful.

This problem has been bothering me for three days. Is there any expert who has encountered the same problem and solved it?

Figure 1

Figure 2

Figure 3

Jacktang

What is the Ethernet external clock setting? Is it related to the system clock setting?

nmg

Is there something wrong with the model you wrote: GD32F307CBT6

I asked the person in charge of GigaDevice's product line, and he said that there is no F307CB model. F307 starts with LQFP64 flash256k. The model you mentioned is wrong.

lerm

nmg Published on 2021-6-25 14:11 Is there something wrong with the model you wrote: GD32F307CBT6? I asked the person in charge of the GigaDevice product line, and he said there is no model F307CB, ...

Thanks for the reminder! I wrote it wrong, it should be GD32F307RCT6. It is LQFP64, 256K+96K, CL series

lerm

Jacktang posted on 2021-6-25 14:02 What is the Ethernet external clock setting? Is it related to the system clock setting?

The MCU is connected to a 25M crystal oscillator, and the Ethernet clock configuration is as follows:

/* choose PLL2 to get 50MHz from 25/5*10 on CKOUT0 pin (PA8) to clock the PHY */
rcu_pll2_config(RCU_PLL2_MUL10);
rcu_osci_on(RCU_PLL2_CK);
rcu_osci_stab_wait(RCU_PLL2_CK);
rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2 );
gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII);

nmg

I asked your question to the group, @donatello1996 guess: the demo provided by the original manufacturer has been tested before leaving the factory, maybe he filled in the wrong port

lerm

nmg posted on 2021-6-25 17:58 I asked your question to the group. @donatello1996 guessed: the demo provided by the original manufacturer must have been tested before leaving the factory. Maybe the port was filled in incorrectly...

OK, thank you! Which group should I go to?

In addition, the official l routine I use is this version: GD32F30x_Demo_Suites_V2.1.0.rar, and the demo is marked with the GD32307C series of microcontrollers. I wonder if it is directly compatible with the microcontroller I use (GD32F307RCT6)?

nmg

This is what the EEWord review group said, but because we don't have your board, we can't confirm the problem. I asked the original manufacturer for you, but there is no feedback yet.

lerm

nmg posted on 2021-6-25 22:37 This is what was said in the EEWord review group, but because we don’t have your board, we can’t be sure of the problem. I asked the original manufacturer for you, but there is no feedback yet

Hello, has the manufacturer responded yet? Can you provide their contact information?

nmg

lerm posted on 2021-6-30 09:48 Hello, has the manufacturer responded? Can you provide their contact information?

Wait for them to contact you, and share it on the forum after you solve it.

lerm

nmg posted on 2021-6-30 11:18 Wait for them to contact you, and share the solution on the forum.

Issue resolved:

1. The MCU needs to be connected to an external 25M crystal oscillator (I originally connected an 8M crystal oscillator, which resulted in failure when using __SYSTEM_CLOCK_120M_PLL_HXTAL);

2. The PA1/RMII_REF_CKL pin of the MCU and the clock pin of the PYH chip are used as clock input pins. They need to be connected to the PA8 pin of the MCU (the routine uses PA8), and then PA8 outputs a 50MHz clock signal to PA1 and PHY, and then initializes according to the default of the routine;

The problem I encountered was mainly the second point. After adding the relevant clock signal, SWR can be cleared normally! As shown in the figure below, the left side is my circuit, and the right side is the official development board circuit:

Note:

1. Regarding PHYIC, the official routine uses DP83848, and I use LAN8702A;

2. If you are using LAN8702A, remember to change PHY_TYPE to LAN8700 in the example program;

3. The clock input pin of DP83848 is pin34, X1; the clock input pin of LAN8702A is pin5, CKLIN;

4. The clocks of PA1 and PHY can be provided by an external 50M crystal oscillator, but it is more direct to use the MCU pin to directly output the clock signal;

5. The PHYAD0 pin of the PHY is the address pin of the module. If it is left floating or pulled down, the PHY_ADDRESS in the routine needs to be changed to 0. If it is pulled up, it needs to be changed to 1.

Finally, thank you @nmg and Mr. Wu from the original factory for your patient answers. Thank you very much!!

soso

Like. :) Looking forward to more exchanges