Hardware Design of a High-Precision Intermediate Frequency Signal Data Acquisition Card

0 Introduction
The main function of traditional data acquisition cards is to complete the baseband digitization of analog signals. Since digitization is performed at baseband, its down-conversion and filtering are all done in analog mode. Therefore, for communication systems with different frequency bands and different modulation modes, special hardware structures should be used. However, such systems lack flexibility, and with the improvement of system sampling rate and sampling accuracy, real-time data transmission has also brought great difficulties.
Software radio is a new radio technology that has emerged in recent years with the emergence of microelectronics and computer technology. The ideal software radio system emphasizes the openness and programmability of the architecture, focuses on reducing hardware circuits with poor flexibility, and places digital processing (A/D) as close to the antenna as possible, striving to change the hardware configuration structure through software updates, in order to solve the problems existing in traditional data acquisition cards. Combined
with the idea of ​​software radio, the data obtained after AD sampling can be directly sent to the digital down-converter, and then the internal registers of the digital down-converter can be reconfigured by changing the FPGA program, thereby completing the digital down-conversion function. This method not only improves the flexibility of the system, but also can well meet the system's high real-time requirements for data transmission.

1 Characteristics and defects of traditional data acquisition cards
The structure of traditional data acquisition cards is generally shown in Figure 1. The characteristics of traditional data acquisition cards are that the analog input signal is first subjected to analog mixing and quadrature demodulation, and the mixed signal is passed through an analog low-pass filter before AD sampling. Since it is difficult for the two analog multipliers and low-pass filters to be consistent, the amplitudes between the I and Q channels obtained after sampling are often unbalanced, and the phase quadrature error is large. At the same time, with the increase of analog input frequency, the sampling rate design requirements for analog low-pass filters and AD devices are also getting higher and higher. In addition, with the increase of sampling rate and sampling accuracy, the data transmission rate of existing PCI, PCI-E and other interface specifications is also difficult to meet the design requirements.

2 Design Idea of ​​New Data Acquisition Card
As an important part of digital receiver, data acquisition should have good flexibility and scalability in processing bandwidth and data transmission rate, but traditional data acquisition cards are difficult to meet these requirements. Based on the advantages of digital signal processing, the analog intermediate frequency input is first sampled by AD, and the data obtained after sampling is sent to the digital down-conversion device for digital down-conversion processing, and then the data is read into the host computer through the PCI bus. Figure 2 shows the structural block diagram of the new data acquisition card.

Compared with analog I, Q quadrature demodulation, digital I, Q not only saves an ADC, but more importantly, the multiplier and filter functions of the two branches can be flexibly implemented in the digital domain through the writing of algorithms, and can be completely consistent, thereby effectively improving the image suppression ratio, and the digital filtering performance is also higher than the analog filter. At the same time, the sampling data is down-converted by a digital down-converter, which can also reduce the data flow rate, thereby meeting the requirements for real-time processing of subsequent data. Therefore, digitizing the input signal at the intermediate frequency or even the radio frequency is of great significance to the development of the data acquisition system.

[page]

3 Design of a new intermediate frequency data acquisition card
Figure 3 shows the overall structure of the new data acquisition card. As shown in Figure 3, the acquisition card structure mainly includes AD sampling, DDC processing, FPGA logic control, cache and interface.

3.1 AD sampling
This acquisition card requires a sampling accuracy of 14 bits and a sampling rate of up to 100MSPS. For this purpose, the AD6645 of Analog of the United States can be selected. In order to ensure 14-bit accuracy, the clock signal of the AD6645 should be provided by a clock source with high stability and extremely low phase noise. At the same time, in order to achieve the best performance, the clock of the AD6645 should also use differential input, because the differential input method can improve the suppression of high-order harmonics, and at the same time, it also has a high suppression ability for common-mode signals such as parasitic noise on the power supply or ground line and local oscillation caused by feedback.
In addition, the data obtained after AD sampling can enter the FPGA in two ways, one of which directly enters the FPGA and is processed after the sampled data enters the FPGA; the other way passes through the digital down-converter, and the sampled data is down-converted before entering the FPGA.
3.2 Digital down-conversion
The main function of digital down-conversion is to down-convert the intermediate frequency signal obtained by A/D sampling and move it to the baseband. It mainly uses a numerically controlled oscillator (NCO) to generate sine and cosine local oscillator signals with the same frequency as the input intermediate frequency signal, and then performs low-pass filtering on the result after mixing to complete the down-conversion operation of the intermediate frequency signal. GC4016 is a chip specially launched by Graychip for digital down-conversion. The chip has four independent identical down-conversion circuits built in. It can down-convert a real sampling signal up to 90 MHz to any frequency. Its internal decimation filter can also reduce the output rate to 1/32 to 1/16384 times the sampling rate. The overall block diagram of GC4016 is shown in Figure 4. The interleaved switch in Figure 4 is used to control the corresponding relationship between the input data and the down-conversion channel.

From a functional point of view, the digital down converter mainly consists of two parts. The first part is the digital controlled oscillator (NCO) and the mixer, which are mainly used to move the digitized intermediate frequency signal to the baseband; the second part is the multi-stage extraction to obtain the desired carrier frequency.
It can be seen that the DDC extraction part is composed of three FIR filter cascades, one of which is a cascaded integrator comb (CIC) extraction filter, and the other two are programmable extraction filters with an extraction factor of 2. The CIC filter has a relatively simple structure, with relatively few multiplication operations. It only uses addition and delay operations. It can perform rough low-pass filtering on the signal and is suitable for processing high-speed digital signals. In addition, the extraction factor is programmable, which is the key to meeting the passband frequency parameters and multi-rate processing, and can reduce the complexity of the post-stage filter. Of course, because it is a coarse filter, its amplitude response is not ideal, and it may also attenuate the useful signal in the passband. Following the CIC filter is the compensation FIR filter (CFIR), which has a relatively simple structure and only 21 orders. Its main function is to compensate for the fading caused by the previous CIC filter, and to further low-pass filter and decimate the signal by 2. The last cascade is the programmable FIR filter (PFIR), which has the most complex structure and 63 orders, so it is generally placed in the final stage to process low-speed signals. It can decimate the signal by 2 and improve the filtering effect.
In general, CFIR and PFIR are both linear phase filters, and they have good characteristics in data conversion.
After the signal is mixed and filtered, it is resampled. Resampling will filter independently and change the output data rate of each channel. Resampling is usually used to increase the sampling data rate to match the word rate and bit rate required by the external circuit.
GC4016 can increase the bandwidth of the output signal by merging channels, that is, increase the data rate. That is, A and C can be merged into one channel, and B and D can be merged into one channel. The output data rate after merging is twice the original. Usually, the maximum bandwidth can be increased to 4 times the original.

[page]

3.3 FPGA logic control
FPGA is the core module of this acquisition card, which can be composed of clock and trigger source control, DDC control, data processing, FIFO storage control and other modules. Figure 5 shows its logic control block diagram.

The clock and trigger control module is mainly used to complete the reception and transmission of control commands such as internal and external clock source selection, internal and external trigger source selection, and data path selection;
The DDC control module is the most important and original part of the acquisition card. It mainly completes the control word transmission of the 255 32-bit registers of the GC4016 chip, thereby realizing its internal module functions. Its core control instructions are carrier frequency, phase information, gain control, setting of extraction factors in each filter and resampling, and output mode setting. The data processing module can complete the processing of the last data flag bit and the necessary data merging or decomposition processing, and the FIFO storage control module can generate the control timing of FIFO work. 3.4 Cache and interface Because the data transmission efficiency of the PCI bus interface is very high, while the efficiency of A/D data acquisition is low, in order to achieve high-speed data transmission, this design uses IDT's FIFO chip IDT72T72105 to realize on-board cache. After the sampled data is cached, it is read by the PCI bus interface controller, which can ensure the real-time transmission of data. There are two ways to implement the PCI bus interface. One is to use a dedicated PCI interface chip, but dedicated chips are expensive, have complex functions, cannot be flexibly configured, and are not conducive to system upgrades and optimizations; the other is to design an FPGA based on an IP core. This method is often used when designers only need to use some of the functions of the PCI interface. This design uses the second method to implement data transmission on the PCI bus, and uses FPGA to design the PCL bus. The design of the PCI interface and user logic can be completed simultaneously in a single FPGA. This method can reduce costs, is flexible in design, has high integration, and can reduce resource waste.

4 Experimental results
This system is highly dense, and most chips are BGA packages. Therefore, during layout, attention should be paid to separating the digital part and the analog part as much as possible to avoid interference of the digital circuit to the analog circuit through the distributed capacitance between the lines. In addition, if there is a strong interfering electromagnetic field around the application site, shielding measures should be taken in the analog circuit part. Figure 6 shows the waveform and spectrum obtained by sampling a 3MHz sine signal with a 100MHz internal clock, setting the DDC local oscillator frequency to 2.999MHz, and the decimation factor of the 5th-order differential comb filter to 25 (that is, the total decimation factor is 25x2x2=100).

If the system clock is 100 MHz and the total decimation rate is 100, then the sampling rate of the system for the down-converted signal is 1 MHz, and the signal frequency after digital down-conversion is 1 kHz. According to the Nyquist sampling theorem, using a sampling rate of 1 MHz to sample a 1 kHz signal can completely restore the original signal without distortion, that is, the signal should appear at 1 kHz. However, in order to allow users to intuitively read the frequency of the original signal from the spectrum graph, the signal spectrum graph after the difference frequency plus the local oscillator frequency can be displayed on the spectrum graph. Therefore, the signal that should appear at 1 kHz is moved to 3 MHz. The signal in the figure appears at 3000.015 kHz, which is consistent with the theoretical analysis.

5 Conclusion
Except for the ADC and power conversion chips, all other chips in this system are packaged in BGA. This design makes the whole system compact and highly integrated. The digital down-conversion function of the system is completely realized by reconfiguring the digital down-conversion devices through FPGA, thus improving the flexibility of the system, solving the shortcomings of traditional digital receivers, and reflecting the superiority of software radio technology.