Design of Telemetry Signal Test Platform Based on PXI Bus

In aerospace testing, the telemetry system is an indispensable and important component. Its main function is to measure the internal/external environmental parameters of missiles, satellites, spacecraft and weapon systems, obtain ground test and flight test data, and provide reliable information and basis for fault analysis, command decision-making, safety control and perfect design. The measurement integrated controller is the core of the telemetry system, which mainly includes three parts: the module for receiving CAN data on the missile, the module for measuring and recording various sensor data, and the module for forming PCM code stream. The reliability of the measurement integrated controller is the core factor affecting the telemetry results. Its accuracy is related to the credibility of experimental data during the development and experiment of the missile, and its performance is related to the success or failure of the experiment. In the process of missile development, it is necessary to undergo many tests, which are very expensive, so the measurement integrated controller is required to have high precision and high reliability. How to accurately, objectively and efficiently evaluate the performance of the measurement integrated controller is an important link in the production of the measurement integrated controller. The measurement integrated controller test system is a large-scale application system that integrates automatic signal generation, automatic detection, automatic measurement and data analysis. It is a test system specifically for the detection of measurement integrated controllers.
This test platform is a subsystem in the test system, and it mainly studies how to simulate multiple sensor signals and store PCM code streams continuously without frame loss through the PXI bus.
1 System Design
As shown in Figure 1, the system communicates with the host computer through the PXI bus, and the local bus and PXI bus are connected through the PCI interface circuit. The system has two working modes: self-test mode and normal working mode. In the self-test mode, the system receives SAR and GNSS signals through hardware connection, and internally simulates a PCM code source on a measurement integrated controller, and then displays the read-back data on the host computer.

2 Implementation of PXI bus and interface circuit
PXI is an extension of PCI in the field of instruments. It develops the PCI bus technology defined by the Compact-PCI specification into mechanical, electrical and software specifications suitable for test, measurement and data acquisition, thus forming a new instrument architecture. PXI perfectly combines the high cost-effectiveness of PC and the need for the expansion of PCI bus into the field of instruments. It meets the user's test requirements by adding a trigger bus and reference clock for multi-board synchronization, a star trigger bus for precise timing, and a local bus for high-speed communication between adjacent modules [1].
2.1 Reading and writing of PXI bus
In a PXI bus application system, if a device obtains bus control, it is called a "master device"; and the device selected by the master device for communication is called a "slave device" or "target device". The PXI bus has two operating modes [2]:
(1) Normal mode: The address and data use the AD bus alternately. The address signal is sent first, followed by the reading and writing of data. In normal mode, one transmission process requires 2 to 3 clock cycles (address cycle + write cycle; address cycle + read cycle + read cycle). For a 32-bit wide data bus, the maximum write data transmission speed is only 66 MB/s, while the maximum read data transmission speed is only 44 MB/s.
(2) Burst mode: In this mode, the master device first sends a start address, followed by a series of data signals that imply the address (address sequence increment). If the memory block with a continuous address is transmitted in this way, for a 32-bit wide data bus, the data transmission speed can reach a maximum of 133 MB/s (32 bits) or 266 MB/s (64 bits).
This system uses the burst read and write mode. Figure 2 is the timing diagram of the 32-bit PXI bus in burst mode.

In the first clock cycle of the timing diagram, the master device puts the address on the AD bus and the command to the target device on the C/BE# (command 1 byte enable) pin. The status on the C/BE# pin identifies different types of PXI commands. The operation of the PXI bus is mainly reflected in the PXI bus command. The bus command appears on the C/BE[3::0] line in the PXI address period. The function of the bus command is to specify the transmission type between the master and slave devices. As shown in Figure 2, the first data transmission requires 3 clock cycles, and each clock thereafter completes a corresponding data transmission.
2.2 PXI bus interface implementation
The function of the interface circuit is to realize the conversion between the local bus signal and the PXI (PCI) bus signal, so the basic function of the interface circuit is to complete the conversion of the read and write operation control logic. At present, there are two main interface solutions for the PXI bus: using programmable logic devices and using dedicated bus interface devices.
(1) Programmable logic device implementation: For designers, it is not necessary to implement all the functions in the specification, and using programmable logic devices can flexibly select the functions they need. The PXI bus has strict requirements on the time of loading and transmitting data. At the same time, it is also necessary to configure various registers inside the device. In order to realize relatively complex applications, developers need to have a deep understanding of the protocol. Therefore, the programmable logic device solution is difficult and takes a long time to develop, which is not suitable for small-scale production.
(2) Dedicated PCI interface chip + FPGA implementation: The disadvantage of dedicated PCI interface chip is that it is less flexible, but it supports PCI protocol, which can reduce development time and improve efficiency. FPGA is used to implement the trigger bus, local bus and other functions required by the PXI bus. This design adopts the interface chip solution.
The PXI interface circuit uses the PCI9054 chip to construct the PCI interface. PCI9054 consists of PCI bus interface logic, local bus interface logic, internal logic and EEPROM interface logic. The local interface logic is implemented by programmable logic devices, including address/data signals, I/O read/write signals, memory read/write control signals, wait cycle generation logic and bus control logic [3]. The serial EEPROM uses the 93CS56 chip. In the EEPROM, the most important configuration information of the interface card is stored in sequence. After the board is connected to the PXI slot, when the system is powered on, the PCI9054 first checks the EEPROM and then configures its internal registers according to the values ​​in the EEPROM. Figure 3 shows the configuration information of the PCI9054 registers.

PCI9054 has three working modes: M, C, and J. M mode is suitable for seamless connection with Motorola's RISC processors (MPC850 and MPC860), so when using other types of processors, C or J mode should be used. In this project, the local data bus is 16 bits and the address data is not reused, so the C working mode is selected. The C mode of PCI9054 supports three direct data transmission modes: direct master mode, direct slave mode, and DMA mode. Because the system mainly uses the PXI bus to transmit data to the computer and read computer configuration commands, and the computer is the master device on the PXI bus, PCI9054 adopts the direct slave mode.
3 Design of functional circuits
3.1 Design of signal source
3.1.1 Design of GNSS signal source
In the measurement integrated controller test bench, the GNSS signal source simulates the GNSS receiver. The accuracy of the signal source is conducive to the measurement of the performance of the integrated controller. The GNSS module of the measurement integrated controller uses the frame synchronization pulse to send a data acquisition request signal to the GNSS receiver at the beginning of each frame. After receiving the request, the GNSS receiver transmits 1,000 bits (125 B, high bit first) of measurement parameters to the telemetry device within 8 ms. The telemetry device must complete the data transmission before the next data acquisition signal arrives. The interface circuit is shown in Figure 4. [page]

3.1.2 Design of SAR signal source
The SAR signal source in the measurement integrated controller test bench simulates a SAR compressor, and uses a standard RS-422-A interface to transmit compressed image data (8-bit serial data per byte). The measurement integrated controller sends a data acquisition request signal to the test system every 25 ms. After the data acquisition request changes from high to low for a period of time, the measurement integrated controller simultaneously sends a shift pulse to the test bench. The test bench sends the corresponding data information to the measurement integrated controller based on the data acquisition request signal and the shift pulse signal. The interface circuit is shown in Figure 5.

3.2 PCM code design
The system uses a typical 96×64 PCM code stream with a main and sub-frame structure. The PCM code data signal sent by the measurement integrated controller is the data sent by the CAN bus, which is the data collected in real time for 64 analog signals, and is composed of GNSS and satellite SAR signals. The PCM code stream in the system uses an operational amplifier output method (±2.5 V method) [4-5].
3.2.1 PCM decoding
As shown in Figure 6, the system first converts the PCM data into a level with an amplitude of 0~5 V through AD8138 (AD8138 also has an inversion function). In order to convert the differential signal into a TTL level that the FPGA can process, and to ensure that the signal is effectively isolated and inverted again, an optocoupler is used to receive the differential signal. DC-DC realizes power supply isolation, so that the system can effectively achieve isolation from the measurement integrated controller, thereby eliminating the error caused by transmission interference.

Although the signal is isolated, the PCM input signal still inevitably has various interferences, which will affect the extraction of code synchronization pulses and PCM data. Therefore, a filter module is connected to the input end of the PCM signal in the FPGA. The module uses a high-precision clock with a frequency that is 20 times the PCM code rate (39.321 6 MHz). The PCM code (PCM-IN) must be maintained for at least 5 clks after the jump before it can be output by the filter module (PCM-OUT), otherwise it will be considered as an interference signal and will be filtered out.
Because the ±2.5 V mode only contains data streams, the generation of real-time synchronization clocks is the key to decoding and the main problem to be solved in serial transmission. PCM synchronous transmission sends data signals at a fixed beat, and the signal transmits data at a constant rate (the system uses 1.966 08 MHz), so the relative position between each code element in the data stream is fixed. In order to correctly distinguish the signal code elements from the converted TTL level serial data, the FPGA must first establish an accurate clock signal, that is, a synchronous clock. This allows the sender and receiver to work synchronously, i.e., bit synchronization. In this design, the code synchronization signal is obtained by dividing clk by 20 and extracting the filtered PCM code. In the logic design of subframe synchronization, a fault-tolerant design method is adopted, that is, the subframe or frame synchronization mark is judged for each subframe. The specific method is: first find an EB 90 or 14 6F, and then judge whether the shifted data is EB 90 or 14 6F every 96 bytes. If not, search again; if so, they are considered to be subframes or frame synchronization marks, and each subframe is judged. The advantage of this search is that even if the first misjudgment is made, it will not affect the correctness of subsequent judgments; even if the PCM code is retransmitted after interruption, or due to interference transmission errors, it will not affect the subsequent correct demodulation. This method of cyclically judging the subframe or frame synchronization mark enhances the fault tolerance and error correction capabilities of the PCM code demodulation process. The PCM decoding program flowchart is shown in Figure 7.

3.2.2 PCM Encoding
As shown in Figure 8, the PCM encoding circuit, REF03 outputs 2.5 V and -2.5 V voltages through the conditioning circuit. MAX4649 is a single-pole double-throw switch, and FPGA controls the PCMCLK signal to determine the output PCM code stream.

This design realizes the design of signal source and PCM frame-loss-free encoding and decoding, and communicates with the host computer through the PXI bus. This solution has been successfully applied to the ground test bench of a certain type of aircraft. After testing and debugging, the system works stably without frame loss, meeting the design requirements.