Design of real-time image test device based on LVDS technology

At present, in some missile-borne equipment, due to the large amount of real-time image data collected, a very high transmission rate is required when transmitting data between it and the ground test bench. Traditional image data transmission methods have great limitations. For example, the physical layer interface cannot meet the data transmission speed; the increase in the number of transmission wires caused by the increase in transmission channels leads to an increase in system power consumption and noise. Low voltage differential signal transmission technology (LVDS) provides a possible solution to this problem.
1 Introduction to LVDS Technology
The core of LVDS technology is to use extremely low voltage swing high-speed differential transmission data, which can realize point-to-point or point-to-multipoint connection. It has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation. Its transmission medium can be copper PCB connection or balanced cable. LVDS has been increasingly widely used in systems with high requirements for signal integrity, low jitter and common mode characteristics [1].
Figure 1 is a block diagram of the basic principle of simplex communication of LVDS devices. It consists of a driver, a differential interconnect unit and a receiver. The driver and receiver mainly complete the conversion of signal level and transmission mode. It does not rely on a specific power supply voltage and can be easily migrated to a low-voltage power supply system without changing its performance. The interconnection unit includes cables, differential wire pairs on PCBs, and matching resistors.

2 Overall system design
The system uses a USB interface circuit to realize data transmission between the computer and the FPGA, and uses LVDS serializers and deserializers to build real-time image sending and receiving circuits. The system's principle block diagram is shown in Figure 2.

The working principle of the system is as follows: the computer sends the control command and real-time image data to the FPGA via the USB interface, the FPGA stores part of the real-time image data in the high-speed SRAM, and then transmits the data in the SRAM to the LVDS serializer according to the control command; in addition, the FPGA also needs to send the read-back real-time image data to the computer via the USB interface at a speed of 20 MB/s for processing.
3 System structure composition and implementation
3.1 USB interface implementation
The USB microcontroller used in this system is the EZ-USB FX2 chip CY7C68013 developed by Cypress. The chip integrates 51 single-chip microcomputer core, USB2.0 transceiver, serial interface engine (SIE), 4 KBFIFO memory and general programmable interface modules. These modules ensure that CY7C68013 can achieve seamless and high-speed data transmission with peripheral devices [2]. When users use this microcontroller to transmit data with peripheral devices, they only need to directly use the GPIF interface to realize the logical connection between the peripheral devices to achieve high-speed data transmission. The GPIF interface of CY7C68013 has 16-bit data lines, 6 RDY signals and 6 CTL signals. The RDY signal is a waiting signal, and GPIF can continuously sample the RDY signal. It is usually used to wait for a certain state of the specified signal to appear in order to determine the next action of GPIF. The CTL signal is a control output signal. It is usually used as a selection signal, a non-bus output signal, and a simple pulse signal [3]. In high-speed mode, the data transmission rate of CY7C68013 can reach 480 Mb/s, so 20 MB/s of real-time image data can be transmitted to the computer in real time [2].
The USB transmission part of this system mainly realizes sending the control commands and real-time image data issued by the computer to the FPGA, and sending the read-back real-time image data to the computer. The command signal sent by the computer is transmitted to the FPGA through the PE port of CY7C68013, and the real-time image data is sent to the FPGA or uploaded to the computer through the GPIF interface of CY7C68013. Since the transmission speed of USB and FPGA is inconsistent, two soft FIFOs should be set in the FPGA, respectively for uploading and sending image data.
3.2 LVDS data transmission and reception part
This system uses 10-bit bus LVDS chips SN65LV1023A and SN65LV1224A from TI of the United States to realize high-speed data transmission and retrieval of real-time images. The rate of sending and receiving 10-bit parallel data of both is between 10 MHz and 60 MHz. Since SN65LV1023A will automatically add 1 start bit and 1 stop bit when the data is converted from parallel to serial, the actual rate of serial data transmission is between 120 Mb/s and 792 Mb/s. Both the LVDS serializer and deserializer require an external clock. Only when the two external clock frequencies are synchronized can the serializer and deserializer communicate normally. Using the internal timing logic of FPGA, the problem of working clock frequency synchronization can be completely solved. [page]

The real-time image transmission and reception circuit is shown in Figure 3. According to the computer control command, the FPGA first reads 1 B of data from the high-speed SRAM, and then outputs the byte plus two identification bits, a total of 10 bits of parallel real-time image data, to the SN65LV1023A. The converted high-speed serial differential signal is then driven by the high-speed cable driver CLC006 for remote transmission. CLC006 can drive 75 Ω transmission lines at a maximum data rate of 400 Mb/s, and also has controllable output signal rising and falling edge times, which can minimize the jitter introduced by transmission. By adjusting the resistance values ​​of R25/R27 and R26/R28, a normal input signal is provided to the driver. The value is selected according to the chip data interface connection part, and it changes with its input level type and impedance transmission line. The signal output amplitude of the driver increases with the increase of the resistance value between Rext-H and Rext-L. In order to achieve optimal signal transmission, the resistor R36 between Rext-H and Rext-L is connected as a 10 kΩ adjustable resistor. The resistance value of R36 is adjusted according to actual conditions to adjust the output signal amplitude range.

Since the transmission line has signal loss and is prone to signal distortion, distortion and symbol crosstalk, this system uses an adaptive cable equalizer CLC014 to equalize the data received after long-distance transmission. CLC014 has automatic equalization, carrier detection and output mute functions for coaxial cables and twisted pairs, and is applicable to data rates ranging from 50 Mb/s to 650 Mb/s, and has extremely low jitter performance.
Although the LVDS receiver provides reliability design for input floating, input short circuit and input mismatch, when the driver is tri-state or the LVDS receiver is not connected to the driver, the connecting cable will produce an antenna effect, and the LVDS receiver may switch or oscillate. To avoid this situation, the transmission cable uses a twisted pair shielded cable; in addition, pull-up and pull-down resistors are added in the circuit design to improve the noise tolerance of the LVDS receiver. R31 in Figure 3 is a matching resistor of 100 Ω, and R32 and R30 are pull-up and pull-down resistors for improving noise tolerance, with a resistance value of 1.5 kΩ.
FPGA mainly transmits and receives data by controlling the TCLK and TCLK_R/F pins of the LVDS serializer and the RCLK and RCLK_R/F pins of the LVDS deserializer. The specific implementation method is as follows: the TCLK and RCLK pins are assigned the same clock (clock frequency is 20 MHz) by the FPGA. At the rising edge of the clock, the FPGA first sends out the 1 B data read from the high-speed SRAM. In addition, after the FPGA receives the 1 B data, it first stores it in the internal FIFO. When the data in the FIFO reaches 512 B, it notifies the USB microcontroller to read the data and then sends it to the computer.
4 Experimental results
Figures 4 and 5 are a frame of 512×512 B (each byte represents a pixel) image data sent and received by the system at a speed of 20 MB/s. The analysis results show that the image data sent and received are completely consistent, meeting the design requirements of the system.

By combining LVDS technology with FPGA, high-speed data transmission between missile-borne image acquisition equipment and ground test bench is realized. The transmission rate of the system can reach 20 MB/s, and the reliability and integration of the system are improved. In addition, the timing of the entire system is controlled by FPGA, which has strong reconfiguration. This design has been successfully applied to the test of a CCD image acquisition device, and the system performance is stable.
References
[1] Wang Bing, Jin Xueming. LVDS technology and its application in multi-channel high-speed data transmission [J]. Electronic Technology Application, 2003, 29(3): 55-57.
[2] Lin Gangyong, Ma Shannong, Xu Banglian. Application of CY7C68013 in data transmission [J]. Microcomputer Information, 2007(10): 76-78.
[3] Xu Zhijun, Xu Guanghui. Development and application of CPLD/FPGA [M]. Beijing: Electronic Industry Press, 2002.
[4] Zhang Guoxiong, Measurement and Control Circuit [M]. Beijing: Machinery Industry Press, 2006.