Practice | How to implement PCIe Gen3/Gen4 receiver link equalization test?
This is a series of introductions on how to implement link equalization testing at the PCIe Gen3/Gen4 receiver end . Xiaotai will explain the working principle of link equalization of PCIe 3.0/4.0 and the testing and debugging of link equalization from theory to practice.
The previous theoretical article ( click here to review ) mainly focused on the working principle of link equalization of PCIe 3.0/4.0 .
This issue is a practical chapter and will focus on the testing and debugging of Rx link equalization . Tektronix's automation software provides the industry's best solution for this.
The contents of the receive link equalization test (Rx LEQ) chapter mainly include:
1) Calibration of stressed eye diagram
2) Enter loopback mode
3) Perform bit error rate test
(Due to limited space, please scan the QR code below for a detailed introduction to the above three parts~)
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Receiver Link Equalization Test (Rx LEQ)
In the era of PCIe 2.0, as long as the signal quality of the transmitting end is guaranteed, the entire system can usually work normally, so the receiving end test is not a mandatory item.
However, in PCIe 3.0/4.0, since the rate increases exponentially and is transmitted over long lines, complex equalization technology is used at the receiving end. Therefore, receiving end testing is a must in PCIe 3.0/4.0.
Tektronix's BSX series of bit error testers are high-performance serial bit error testers in the industry, capable of achieving up to 32Gbps code generation and bit error analysis functions . At the same time, it has internally integrated pre-emphasis modules , noise injection , jitter injection , etc., and supports protocol-based handshake functions.
Therefore, it is very suitable for PCIe 3.0 and 4.0 receiver testing. Since the BSX series supports up to 32Gbps, it can also fully meet the requirements of future PCIe 5.0 receiver testing. Figure 1 is a schematic diagram of using the BSX series bit error tester to perform PCIe 3.0 receiver testing.
Figure 1. Schematic diagram of PCIe 3.0 receiver test
The receiver of PCIe 3.0 & 4.0 integrates complex units, such as equalization circuit, clock recovery circuit, and decision circuit, which cannot be directly detected. Therefore, the receiver is a black box for testers. In the face of this difficulty, the specification developers of the PCI-SIG Association developed a methodology called "Stressed Eye" to complete the evaluation of the receiver.
The core idea of this methodology is to apply a severely degraded signal (i.e., stress eye diagram) to the receiver to detect whether the receiver can still receive the signal correctly under such circumstances. Therefore, the test of PCIe 3.0 & 4.0 Rx LEQ can basically be broken down into three steps: stress eye diagram calibration, entering loopback mode, and performing bit error rate testing.
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Calibration of stressed eye diagram: It includes quantitatively specifying the extent to which the degraded signal degrades (specification requirements), the steps by which the degraded signal can be generated (generation method); how to determine whether the generated degraded signal meets its specification requirements (measurement method);
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Enter loopback mode: In order to detect whether the receiving end receives the signal correctly, it is necessary to loop the received signal back to the transmitting end to be tested intact; then the bit error tester judges the looped signal. Therefore, it is necessary to put the device to be tested into loopback mode;
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Perform bit error rate test: Use the specified code type to perform bit error rate test.
Figure 2. Tektronix PCIe Rx Automation Software GUI
When calibrating the stressed eye diagram, it involves signal characteristic analysis and adjustment iteration, which need to be repeated. Manual operation is very time-consuming and thankless. To this end, Tektronix provides the industry's best PCIe Rx automated test software (BSXPCI4CEM) , as shown in Figure 2. Tektronix's PCIe Rx automated test software can greatly shorten the development time of developers and improve product reliability.
In actual Rx LEQ testing, it is often impossible to enter the loopback mode due to various reasons; or even if it enters the loopback mode, there are still many bit errors. At this time, we need to go beyond consistency testing and perform a series of debugging work to find the root cause.
In addition to providing the compliance test required by the association , Tektronix's PCIe Rx automated test software also provides a wealth of debugging functions . Combined with the general debugging functions of the BSX series bit error tester , it can provide users with full flexibility.
Figure 3. Using the eye diagram function of a bit error tester to observe the signal quality of the loopback data output of the object under test
When performing the Rx LEQ loopback test, there are two data paths: the receiving data path and the loopback data path. Since Rx LEQ is a test for the receiving data path, the user must ensure that the DET of the BERT will not be misjudged due to the loopback data path. Tektronix's BSX series BERT has a rich eye diagram test function , as shown in Figure 3. In this way, users can debug bit errors without making any topology changes.
Figure 4. Loopback settings in the automation software
Users can use the "Empty A - Modified Compliance B.ram" file provided by Tektronix to enable the DUT to stably enter the Compliance mode, and then use this ram file to switch the code pattern, switch the output of the DUT to 8Gbps or 16Gbps, and observe which preset value can give the best eye diagram. Then, set "Preset/Hint" in Figure 4 to the preset setting just now, which can ensure that the loopback data path will not introduce misjudged bit errors .
Figure 5. Bit error rate test of scanning the coefficient space of Tx EQ
If the bit errors caused by the misjudgment introduced by the loopback data path are eliminated, there are still bit errors in the Rx LEQ. At this time, the user needs to further analyze the source of the bit errors, for example, whether the DUT's equalization algorithm is not optimal, so it does not request the optimal Tx EQ value from the link peer. At this time, the user can use the "BER Test" provided by Tektronix to scan the entire coefficient space (as shown in Figure 5) . If the measured results show that there are some coefficient combinations in the coefficient space that can achieve no bit errors, then it means that the DUT's equalization algorithm is not optimal.
On this basis, users can also perform margin testing. Tektronix's automated software provides margin testing for Sj and DMSI , as shown in Figure 6 and Figure 7.
Figure 6. Margin test for sinusoidal jitter:
(a) Setting interface (b) Scan test interface
Figure 7. Margin test of differential mode noise:
(a) Setting interface (b) Scan test interface
Tektronix provides the industry's best consistency solution for PCIe 3.0 & 4.0 . By using Tektronix's high-performance oscilloscopes, high-performance bit error testers, and flexible automation software, users' development time can be greatly shortened, making their products more competitive in the market.
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