I3C standard, new milestone

Today's electronic devices rely heavily on data and communication with other electronic systems, necessitating newer and better communication standards and protocols. One such protocol is the improved inter-integrated circuit (I 3 C) standard, which is built on I 2 C to provide unprecedented reliability and functionality.

In June, the MIPI (Mobile Industry Processor Interface) Alliance organized its annual Plugfest. This year's event represents an important milestone in the I 3 C standard. This week, the MIPI Alliance announced the results of the Plugfest. So what happened at this year’s Plugfest? What exactly is I 3 C?

I3C Plugfest is a well-known event organized by MIPI to promote the adoption and interoperability of I3C designs. The event, held this year in San Jose, California, was attended by 26 I3C implementers representing 10 companies, including industry leaders such as Intel, STMicroelectronics and Microchip Technology.

This year's Plugfest focuses on rigorous interoperability testing across multi-vendor devices, covering the entry-level to advanced stages of I3C design. As part of this, the event involves a confidential environment where participants can test interoperability between multi-vendor controllers and target devices.

Specifically, three key I 3 C specifications were tested:

MIPI I3C: The mature MIPI I3C specification is a comprehensive version designed to be the successor to I2C. It combines the key attributes of traditional I 2 C and SPI interfaces to provide a powerful and flexible upgrade path.

MIPI I3C Basic: A simplified, royalty-free subset of MIPI I3C that bundles the most commonly used features. It is designed to be simpler and easier to implement, making it ideal for less complex systems or companies looking to transition from I2C to I3C without a steep learning curve. MIPI I 3 C Basic has been adopted by JEDEC's sideband bus and DDR5 standards, demonstrating its usefulness in a range of applications.

MIPI Debug for I 3 C: This specification focuses on debugging and testing capabilities. It provides a bare-metal interface that allows system designers to debug and test application processors and other power management components in the system through the I 3 C interface.

Because each specification addresses different needs and use cases, MIPI sees Plugfest as a truly comprehensive testing ground for I3C's versatility.

I3C is a high-speed, low-power bus interface developed by the MIPI Alliance. I3C was designed as an evolution of the traditional I2C and SPI interfaces to provide a unified, scalable solution for connecting peripherals to application processors.

I3C operates on a two-wire interface, similar to I 2 C, consisting of a data line (SDA) and a clock line (SCL). However, unlike I 2 C, it includes some advanced features that make it unique.

For example, I3C supports higher data rates, up to 12.5 Mbps, while I2C's maximum data rate is 1 Mbps. It also introduces new bus events and timing modes, such as In-Band Interrupt (IBI) and Common Command Code (CCC), allowing devices to communicate with each other more efficiently. In addition, I 3 C adopts a dynamic addressing scheme, supports device hot connection, and supports multi-master configuration, making the bus more elastic and flexible.

The importance of I3C lies in its ability to serve as a comprehensive interface for a variety of applications ranging from smartphones and wearable devices to automotive systems. Its high data rates and low power consumption make it ideal for battery-powered devices where energy efficiency is critical, while its backward compatibility with I2C ensures that existing systems can transition to I3C without a complete overhaul.

On the other hand, the successful completion of Plugfest is an important milestone for the I 3 C ecosystem. It not only validates the interoperability of I 3 C devices but also accelerates its adoption as a standard. As industries continue to demand faster and more efficient communication protocols, the I 3 C standard, backed by successful interoperability testing, is well-positioned to meet these challenges.

Microchip Technology, a leader in I3C integration, has launched the PIC18-Q20 family, the industry's first low-pin-count MCUs with up to two I3C peripherals and multi-voltage I/O (MVIO).

Available in 14-pin and 20-pin packages as small as 3 x 3 mm, PIC18-Q20 MCUs are a compact option for real-time control, touch sensing and connectivity applications. MCUs provide configurable peripherals, advanced communication interfaces, and easy connectivity across multiple voltage domains without the need for external components.

As data collected and transmitted from cloud-connected edge nodes increases, improved inter-integrated circuits (I3C) are quickly becoming a more sustainable option for connecting sensors with high data rates and will help expand future capabilities. . Power Equipment.

With I3C functionality, flexible peripherals, and the ability to operate on three independent voltage domains, the PIC18-Q20 MCU is ideally suited for use in conjunction with a host MCU in a larger overall system. This family of MCUs can perform tasks that the main MCU cannot perform efficiently, such as processing sensor data, handling low-latency interrupts, and system status reporting. Although the CPU operates in a different voltage domain, the I3C peripherals operate from 1.0 to 3.6 V. These low-power, small form factor MCUs are used in a variety of space-sensitive applications and markets, including automotive, industrial control, computing, consumer, IoT and medical.

"One of the major barriers to mass adoption of IoT is the cost of implementing edge nodes. With the PIC18-Q20 family, Microchip is helping to break down this barrier," said Greg Robinson, corporate vice president of Microchip's 8-bit MCU business unit. "By introducing the industry's first low-pin-count MCU with I3C, we can flexibly and cost-effectively expand IoT applications and adopt new standard communication interfaces."

As the market shifts to require higher performance, lower power consumption and smaller size, I3C helps designers and software developers address these potentially challenging requirements.

I3C offers higher communication rates and lower power consumption than I2C while maintaining backward compatibility with legacy systems. I3C and MVIO functionality combined with Microchip's configurable Core Independent Peripherals (CIP) can reduce system cost, design complexity and board space by replacing external level translators with multiple voltage domains on-chip.

PIC18-Q20 MCUs are supported by a complete development ecosystem of hardware and software tools, including MPLABX and MPLAB Xpress integrated development environments (IDEs) and MPLAB Code Configurator (MCC). Microchip's development environment is simple, making it easier to implement and generate code, reducing overall development time and financial investment.

Developers can quickly start evaluating the I3C and MVIO functionality on the PIC18-Q20 using Microchip's PIC18F16Q20 Curiosity Nano Evaluation Kit, a compact, cost-effective rapid prototyping board.

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