New trends in the chip design industry

It is the consensus of people in the industry that chip design is becoming more and more complex as time goes by, but in what aspects is "complexity" reflected, and as complexity increases, what problems remain unsolved, which requires in-depth investigation. and research. Last week, Siemens EDA and Wilson Research fully announced the chip design report that the two companies will collaborate on in 2022. The quantitative analysis of the report provides us with some important insights. After studying the report, we believe that the chip design becoming more complex is not only reflected in the increase in chip transistor scale, but also in the increase in SoC complexity, and the increase in SoC complexity will bring about a series of changes. Including changes in design methodologies and new requirements for design verification. These new changes and new needs will drive changes in chip design in the next few years.

With the emergence of new applications such as artificial intelligence and smart cars, chip complexity is slowly increasing. The increase in chip complexity can be a multi-dimensional matter. On the one hand, it can be reflected in the increase in the number of transistors; on the other hand, it can also be reflected in the number of complex subsystems in the chip.

From the perspective of the number of transistors in a chip, in the Siemens/Wilson research report, more than 36% of chip projects have gate numbers in the tens of millions, while only 30% of projects have gate numbers below the million level. Therefore, from the perspective of the number of transistors, Angle, the complexity of today's chips has indeed increased significantly.

But transistor count isn't the only consideration. For example, in some chips, on-chip memory (such as cache) can occupy a considerable number of gates, but its overall design complexity may not be very high. Therefore, another way to look at chip complexity is the number of chip subsystems. In an SoC, each chip subsystem has its own unique functions, and when there are more chip subsystems, it is challenging to make these subsystems work well together. Therefore, the number of subsystems in a chip is also an important indicator of the overall chip complexity. However, the number of chip subsystems is not easy to count, and one data that can be linked to this number is the number of processors used on the chip. Usually, when the complexity of the chip subsystem exceeds a certain level, it will be equipped with a separate embedded processor to serve it. Therefore, counting the number of embedded processors on a chip can reflect the number of complex systems on the chip to a certain extent, thereby reflecting the complexity of the chip design.

From the perspective of the number of embedded processors on the chip, first of all, we can see that 74% of today's chips have at least one embedded processor; more than half of the chip projects have more than two embedded processors, and 15% of the chip projects have at least one embedded processor. There are more than 8 embedded processors. From this perspective, today's chip design is indeed becoming more and more complex from a system perspective.

To sum up, we believe that the increase in the complexity of chip design is not only reflected in the number of transistors, but also in the complexity of the system. These increases in complexity are due to application-side drivers (such as artificial intelligence, smart driving, next-generation smart devices, etc.). As these systems become more popular in the future, we expect that the complexity of chip systems will be further increased, which will also Bring corresponding changes to the chip design industry.

The impact of chip system complexity on chip design ecology is multi-faceted. First of all, as mentioned above, as the application is driven, the complexity of the chip system increases, and the number of highly complex subsystems on the entire chip system increases, which also increases the number of embedded processors required on the chip. On the one hand, applications have driven the increase in demand for embedded processors; on the other hand, if there are embedded processors with lower costs and more flexible designs, they will be able to further enable this increase in complexity.

From this perspective, RISC-V can be said to have met the need to increase the complexity of chip design. It is expected to be increasingly used in the future, and from another perspective, it will increasingly meet the needs of embedded chip systems in complex chip systems. processor requirements. RISC-V is an open source processor instruction set that anyone can freely use and further customize additional instruction sets to meet their own needs. For powerful manufacturers, they can use the RISC-V instruction set to independently develop their own processors and use them in their own products; while for small and medium-sized manufacturers, they can also choose RISC-V processor IP provided by SiFive and other companies. to use. Currently, using RISC-V as an embedded processor/MCU that does not require high computing performance has become the choice of more and more chips. The main reason behind this is the cost and flexibility of RISC-V-based processors. Siemens/Wilson's 2022 chip design report further confirms this view: 30% of chips will use RISC-V processors in 2022, while this number was only 23% in 2020. In the future, we expect RISC-V to be further widely used, and on the other hand, it will further enable the complexity of chip systems.

In addition to embedded processors, as the complexity of chip systems increases, another change in chip system design is how to connect these systems together in an efficient and reliable way so that they can communicate with each other and access memory. This requires the increasing use of NoC (network-on-chip). NoC will increasingly become the basic IP on SoC systems to ensure that chip system design can expand its complexity and design scale more efficiently. According to market research company Brainy Insights, the compound annual growth rate of NoC will reach 7.9% in the next ten years, so we also expect to see the use of NoC in more and more large-scale and high-complexity chips in the future.

Therefore, we believe that from the perspective of design IP, new embedded processors (RISC-V) and on-chip interconnection (NoC) will become important new perspectives to drive and enable further improvements in the complexity of chip systems.

In addition to new design IP, verification of complex chips will become another challenge. As mentioned before, complex chips include more and more subsystems. First, the verification of each subsystem will become more and more challenging as its complexity increases. Secondly, the collaborative work and verification of multiple complex subsystems will become another difficulty in chip verification. Finally, there is heterogeneity in each subsystem in the chip system. For example, high-performance analog/mixed-signal modules (such as memory interfaces, etc.) are increasingly used in complex chip systems, which also brings challenges to the verification of the overall chip system. challenges because the verification methods of different subsystems are not consistent.

Chip verification first needs to improve efficiency and reduce the time required. According to the Siemens/Wilson report, up to two-thirds of chip projects in 2022 failed to be delivered as scheduled. This also shows that the current chip verification system still needs more efficiency improvements for complex chips.

In addition, the proportion of successful first-time tape-outs of chips is also declining, with up to 76% of projects requiring two or more tape-outs in 2022 to achieve design goals. Among the reasons that cause chips to need to be taped out multiple times, the primary reason is logic function problems, and another noteworthy reason is problems with analog modules: this project accounts for 10% of the total in 2020 and 2022, up from 20% a few years ago. It has jumped to 40%, which also shows that verification related to analog design and collaborative verification of analog modules and other modules will become very important issues that need to be solved in the field of complex chip verification in the future.

Looking to the future, the verification of complex chips first requires a more efficient verification process, such as using a more efficient testbench description language (using C++/Python, etc.) to ensure that chip projects can be delivered regularly. In addition to efficiency, since logic function is still the primary problem in chip tape-out failure, and as the complexity of chip systems increases, this problem will become larger and larger. Therefore, reliable verification methods (such as emulators) are required. The emulator needs to be able to further reduce costs and improve support for complex systems to ensure the quality of complex chip systems. Finally, simulation verification is expected to become a key part of future complex chip systems. This includes simulation verification and collaborative verification of analog and digital systems (for example, analog system modeling is put into digital systems for verification, etc.), which is very important for new verification. The adoption of methodologies and new EDA systems have raised new demands and are expected to become another highlight in the field of verification in the next few years.