Subverting EUV lithography? Don’t let ASML be the only beauty!

First, there is a lot of disdain for this tool from people in the semiconductor and financial industries, despite having a very clear use case. Some argue that this is nothing new, it's just a very expensive form of inductively coupled plasma used to do reactive ion etching, which has been around for decades in high-volume manufacturing. One could also argue that lithography has been around for 150 years and EUV is nothing new. shaping is obviously unique.

Another major objection is that it's immature and far away. That's wrong too. Although Sculpta was only officially announced last week at SPIE's Lithography and Advanced Patterning conference, the new tool has been a long time coming. Applied Materials has been publishing public research papers on this tool type since at least 2015.

The company's first customer has been working with Applied Materials since 2017 to develop the tool. Applied Materials even conducted a technology demonstration at last year's SPIE Advanced Lithography & Patterning conference and provided real customer test data.

There’s an interesting story about this particular presentation. After the Applied Materials presentation, we left the presentation room and spoke with some of the attendees. The general consensus is that it's pretty cool, but it doesn't work. Why? Company speeches participating in SPIE are divided into 3 categories. 1. What is about to go into production, 2. What is years away with a stake planted in the ground, 3. What is not working at all but is showing up because there is nothing else to do with the data. Our hypothesis last year was that Applied Materials' technology was between care #2 and/or #3.

Now it turns out that was a wrong assumption.

Applied Material's Centura Sculpta isn't some crazy technology that's completely immature and far from production. Sculpta is real, it works, and it will generate hundreds of millions of dollars in revenue over the next few years. Given that it is advertised as directly removing EUV double patterning in the first use case, let's first quickly review the lithography multi-patterning process.

Photolithography is a core process for high-volume semiconductor manufacturing. Once you overcome the limitations of lithography tools, you can still continue to scale individual feature sizes by moving to various multi-patterning schemes. Below is a simplified description of “litho-etch-litho-etch (LELE: litho-etch-litho-etch)”, one of the most common multi-patterning schemes. For the sake of simplicity, we will put other schemes such as SADP and LELB into the same bucket as LELE.

The LELE process flow goes through two complete photolithography cycles to achieve tighter feature sizes than a single patterning step. The entire cycle can be dozens of different process steps, including hard mask deposition, underlayers, mid-layers, SARC, CMP, cleaning, stripping, spin coating, baking, developing, exposing, Etching and the various metrology/inspection steps in between.

The key is that going from a single lithography cycle to a LELE process involves doubling the cost of lithography and the many other tools involved in the process.

Applied Materials specifically targets EUV multi-patterning reduction as the first use case for Sculpta. They claim they can achieve the same feature fidelity as LELE with a single photolithography cycle and Sculpta.

According to Applied Materials, they estimate approximately 25 kWh per wafer, approximately 0.5 kg CO2 equivalent emissions per wafer, and approximately 15 liters of water per wafer per LE (photolithography) cycle. In the right box we show the cost. We estimate monthly capital costs per 100,000 wafers to start up at approximately $350 million and operating costs per wafer fabricated or per EUV cycle of approximately $70 per wafer. By adopting Applied Materials' new technologies, we estimate that we can save approximately $250 million in capital costs per month per 100,000 wafers launched and approximately $50 in manufacturing cost savings per wafer.

As can be seen from the above, the cost, power, water and CO2 savings claimed by Applied Materials are substantial. TSMC has increased its 7nm and 5nm node production capacity to (approximately) 200,000 wafers per month. Per tier, this will save them $500 million in capital expenditures and more than $100 million in annual operating expenses.

TSMC 5nm features EUV multiple patterning steps. TSMC 3nm contains multiple EUV multi-patterning steps. The technology targets the insertion of “2nm” class nodes that may include more than 10 EUV multi-patterning steps without the need for Applied Materials Sculpta pattern shaping. If you assume that Sculpta can be used *anywhere*, then using Sculpta could save *billions* of dollars per year.

However, we need to reiterate that this analysis is too simplistic because we cannot use pattern shaping everywhere. We'll share where and how to use it, but first let's talk about what Sculpta and pattern sculpting is.

At the heart of Centura Sculpta is the ability to perform a new type of step called pattern shaping. Pattern shaping involves emitting a strip-shaped plasma beam toward the wafer at a certain angle. Compared to the wafer, the angle can be controlled between 0 and 70 degrees. The zero angle is 90 degrees to the angle of the wafer.

The plasma beam travels in one dimension to keep the process uniform across the wafer. The purpose is to extend the feature in one direction. Pattern shaping can be performed in any direction by rotating the wafer and passing the beam through the wafer again.

It is critical that pattern shaping does not affect the critical dimensions of the silicon features that need to remain unchanged. This means that it is critical to only change features on one axis. Applied Materials says that for every 1 unit of length in the other direction, they can change a single dimension by 20 units of length.

This is highly selective in direction. The fab can also control how much the pattern is elongated by increasing or decreasing the time spent bombarding the strip beam. Etch time is an important lever that fabs can leverage.

Another consideration in maintaining a uniform shape is ensuring that the beam angle is optimized for the various structures on the wafer.

If the beam angle is not aligned correctly, shadows can be created on structures of different sizes.

If the planarization layer and hard mask have different etch selectivities, the plasma beam will cause the sidewalls to be unevenly straight.

The sidewall profile of the feature must be optimized or performance, power, or yield issues will occur.

The angle of the plasma beam is important for fab optimization to ensure uniform elongation for features of various sizes. Using a higher versus lower angle takes into account factors such as the time required to etch, the erosion rate of the top layer, and the erosion rate of the bottom layer to maintain the integrity of critical dimensions. Each application will have different beam angles and timings. Applied Materials works on a variety of different chemistries so the beam can be used on a variety of hard masks, underlayers and underlayers.

Pattern shaping occurs after development, cleaning and etching of the photoresist and anti-reflective coating.

Once patterning has occurred, pattern transfer etching can be performed. This allows pattern shaping to be used even if you have multiple masking and patterning stages. Pattern shaping can be combined with multiple patterns.

Pattern molding requires more than just developing in the direction of existing features. It can also be done at any arbitrary angle. To us, this seems to be more about the alignment and process control of Applied and Sculpta than a practical use case for asymmetric shaping. We can't think of a use case for asymmetric shaping, but if you think there is, please share.

Now that we've introduced what pattern shaping is, it's time to introduce practical use cases for pattern shaping.

The Scuplta tool has 3 main use cases: tight hole and slot patterns, narrower tip-to-tip patterns, and removing stochastic bridging.

The first application is to use conventional photolithography (LE) methods to obtain hole and groove patterns with tight corner-to-corner dimensions, which requires multiple patterning. With pattern shaping, you have the advantage of using only one LE step to get from corner to corner. Tight corner-to-corner is important because it allows you to fit more functionality into the same area. In this case of using vias, performance and power characteristics can be improved since there is more via area.

In the image above, you can see on the left how tight corner-to-corner is achieved using traditional self-aligned LELE technology. You would need 2 different masks to achieve tight corner to corner vias, but with pattern shaping you can use one mask to create all the vias that don't have tight corner to corner, and then shape the vias to make them Has a tight angle - to the corner.

The second application is to produce grooves with a tighter tip-to-tip pattern. This is very similar to the first app, but with a different type of functionality. In this application, graph shaping is used to bring the two sets of lines as close as possible without using a second mask.

On the left is traditional LELE technology. The first mask creates the line, then the second mask creates a split in between to get the tightest possible tip spacing. Patterning allows you to use one mask to create 2 sets of lines with a loose groove in the middle. Sculpta can then remove as much material as possible to make the trench as thin as possible.

The third application is to reduce random bridging defects. A random bridging defect is located on a line where the etch was unable to remove all the material it was supposed to have. Generally, this is because the photoresist layer is also not exposed properly.

These defects cause electrons to go where they're not supposed to go, increasing power. It can also lead to lower yields if the bridge ends up connecting 2 critical layers together causing a short circuit or communication error. Applied Materials says that through pattern shaping, Sculpta can reduce these defects by more than 90%.

In a different presentation, ASML talked about how shrinking the tip beyond 27 nanometers starts to exponentially increase random defects using EUV single patterning. Pattern shaping will help significantly reduce these pattern defects, as the photolithography tool can pattern looser features and turn the sculpta shape into a tighter tip-to-tip. Pattern shaping also helps reduce groove-to-groove defects in the same way.

It should be noted that ASML's data is for a simple process, and the complex wiring used in real chips will use current resistors to push defect walls at 30nm and above.

Metal stacking is one of the most important parts of any process node. It is capable of routing signals around the wafer. The metal stack consists of more than a dozen layers, but the most important layers are the M0 to M4 layers. In terms of the layout of modern process nodes, M0, M2, and M4 are critical metal layers perpendicular to the gate, and M1 and M3 are parallel to the gate.

The metal stacking of a chip is an area where many complex and difficult trade-offs need to be made. The denser and thinner each metal layer is made, the more signal routing can be done, and ultimately, more useful transistors can be packed into any given area. However, this comes at a huge cost.

The thinner the wire is made, the higher the resistance of the wire. Remember Ohm's Law from high school. Ohm's law states that R = (V/I), where R is resistance, V is voltage, and I is current. Although Ohm's law does not fully apply to such small wires, process node integration engineers must grapple with the increased circuit resistance caused by denser metal layers. They can compensate by increasing voltage or decreasing current. The simplified trade-off is that a denser metal stack requires more power to send a signal than a looser metal stack. Shrinking metal spacing is not always a good thing.

Copper is the metal of choice for Intel, TSMC and Samsung's 3nm and 4nm process nodes. For single patterned EUV, ~32nm is approximately the line spacing limit of current resist chemistries and coverage capabilities. For vias, this number is actually higher. For simplicity, assume a limit of 30 nm for EUV single patterning of all features.

This example is oversimplified for demonstration purposes. Pictured above is a single metal layer on a chip. Each 30nm x 30nm cell that can be defined by a single patterned EUV tool can be either copper or an insulator, typically SiO 2 . This isn't how photolithography works, but it's easier to explain.

If EUV single patterning is used, the metal layer may look like the above. There are many wires around it carrying signals from one part of the chip to another. These wires also connect to layers below and above the chip layer we're looking at. In many cases, this layer has vias that pass signals directly up and down to other layers without routing the signals. In this example, since the metal is only 30 nanometers wide, there's a big trade-off in resistance.

This is where multi-patterning comes in. The goal is not to fill more wires, but to maximize the copper area and minimize the SiO2 area. This results in lower resistance when sending signals throughout the chip, resulting in higher performance and power efficiency.

For simplicity, assume that the limit of multi-patterning is now 15 nm instead of 30 nm. In fact, the current limit of LELE EUV is more in the range of ~21 to ~23nm. The upper limit is TSMC's pitch on the M0 metal layer of its N3E process node. The lower bound is the 2nm node we will discuss later. It is important to note that multi-patterning does not directly halve the spacing, as some headroom is given up due to stacking errors and randomness.

If our pixel size were now 15nm, using multi-patterning in this oversimplified demonstrative fictional example, the routing density would remain the same. Instead, this increase in fidelity will serve to deposit proportionally more copper relative to SiO2 . Copper line width was increased from 30 nanometers to 45 nanometers, and tip spacing was also improved. The SiO2 insulator is still present to prevent the copper signals from mixing and shorting the chip.

Increased linewidth and tip-to-tip spacing results in significantly lower resistance and increased power and performance. Note that the transition from single patterning to SALELE or pattern forming does not simultaneously improve tip-to-tip and line spacing, this example is exaggerated and unrealistic to conceptually demonstrate the potential benefits.

In the real world, the benefit is smaller, but necessary, and is one of the primary use cases for pattern shaping. The density of features can already be achieved through single patterning, but the shape of those features cannot. Pattern shaping helps bring lithography-printable features into the desired shapes in the fab.

There are also yield and power trade-offs regarding metal and via layers. Vias are a way to connect different metal layers. Each layer is manufactured and then stacked together perfectly. Craft allowance and stacking determine the ability to stack them perfectly.

Any misalignment can cause one layer to miss the layer below it, thus not making a connection where there should be one (open). Even worse, a metal layer may connect to another layer that it shouldn't, creating an incorrect connection (short circuit). Because patterning is a selective process, fabs can turn directional etching up or down in the direction or amount they need to minimize shorts and opens while maximizing feature size.

The resistance issue is significant, especially at the lower vias where pattern shaping is most applicable. On TSMC's N3E node, more than 90% of the via resistance is caused by V0 to V5.

The next 9 vias are insignificant in terms of via resistance. If the V0 to V5 vias could be made larger and still fit in the same area, then the resistance would be reduced and the density would not be affected.

The trade-off of better fidelity with multiple patterning is good from a power and performance perspective of the metal stack, but it hurts a lot from a cost perspective. The number of process steps per metal layer has almost doubled.

Pattern shaping cannot increase the number of metal layers or vias in a given area, but it can increase their size and reduce tip-to-tip spacing. The first use case is being implemented on a node that will be used for volume production of the metal stack in late 2024/2025.

Also at the SPIE Lithography Conference, Martin van den Brink, ASML's long-term chief technology officer and the life force behind EUV, gave a keynote speech and opening speech. In his speech, Martin talked about the past 15 years and the next 15 years of EUV, as well as our development direction and the goals of ASML.

It's better than European. Although a lot of work is needed to achieve High NA EUV, it is not nearly the same amount of work as the initial launch of EUV. In his presentation, he demonstrated significant reuse of existing EUV technology, so High NA will be more evolutionary than revolutionary. Obviously, some key components, such as the lens, will be completely new, but require more engineering and less pioneering work.

He also talked about a target power of 1,000 watts, which now seems more achievable than previous power improvements. He made some self-effacing jokes about the slight deviation in his previous power timetable estimate (which we clearly remember) and got some laughs from the audience.

Part of getting to 1000 watts is to get to 500 wafers per hour, importantly not just in EUV but also in DUV. ASML is well aware of the price/productivity concerns, which are particularly focused on high-priced lithography tools.

In our opinion, the productivity focus on DUV is well-deserved as it remains the workhorse of lithography.

Productivity is a key element of ASML's pricing strategy. Increasing throughput is a valuable reason to increase pricing. ASML has long used this “value”-based pricing, supporting higher pricing by increasing the number of wafers per hour.

We could joke that increasing productivity by one wafer per hour would be equivalent to a million dollars in additional pricing, and we might not be far off….

The rest of Martin's talk was a wealth of excellent information, facts and figures that went by too quickly to fully comprehend...but was worth a slow replay.

One of the key data points is the power requirement of 100KW (100,000 Watts) per wafer processed by the lithography tool. That's an astonishing number, not just in terms of laser power, but with the increased throughput, it's also able to accelerate and decelerate huge chunks of granite platform incredibly faster.

We have previously noted that fab power needs are a growing problem. That's why Samsung is building its own power plants in Texas because it can't use the unreliable power grid there. Another interesting fact that Martin didn't mention is that TSMC consumes about 10% of the entire island of Taiwan's power grid for its fabs!

From this speech by Martin van den Brink, we have new insights into this new tool of Applied Materials.

*Disclaimer: This article is original by the author. The content of the article is the personal opinion of the author. The reprinting by Semiconductor Industry Watch is only to convey a different point of view. It does not mean that Semiconductor Industry Watch agrees or supports the view. If you have any objections, please contact Semiconductor Industry Watch.

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