Intel Packaging Technology Roadmap

"Semiconductor manufacturing and packaging are converging, and packaging has become a very important and interesting innovation area in this process," said Johanna Swan, director of packaging research and system solutions at Intel.

As we can see, in today's semiconductor market, the few companies that are still committed to the development of advanced processes have begun to expand in the direction of advanced packaging technology. This also means that packaging technology, especially advanced packaging technology, has been regarded by the industry as one of the keys to continue to promote the development of Moore's Law.

At the same time, this integration has also promoted changes in the foundry market. Among them, the changes that have taken place in Intel have attracted the most attention. So, for Intel, what role does packaging technology play, and how do they view the development of packaging technology? It is worth exploring.

As a representative of the IDM model, after the new CEO Pat Gelsinger took office, Intel, a company that has led the development of the semiconductor industry for decades, announced that it would welcome a new era of manufacturing, namely IDM 2.0. Pat Gelsinger once emphasized that in the IDM 2.0 era, Intel's core capabilities are still the integrated capabilities of design, manufacturing, and packaging.

We see that today, as the importance of packaging technology becomes increasingly prominent, the importance of advanced packaging has also been emphasized after Intel announced that it will enter IDM 2.0.

Pat Gelsinger once pointed out that Intel's leadership in packaging technology is an important differentiating factor, which enables Intel to deliver unique and customized products to meet the diverse needs of customers in a world of ubiquitous computing by packaging multiple IPs or chips together.

If Intel's advanced packaging technology was once only available to Intel's products, then in the era of IDM 2.0, Intel's advanced packaging technology is likely to be adopted by more products.

This is thanks to Intel's Intel Foundry Services (IFS). In previous reports, the media described the advantages of IFS as follows: the IFS division is differentiated from other foundry services in that it combines leading process and packaging technologies and supports the production of x86 cores, ARM and RISC-V ecosystem IPs, thereby delivering a world-class IP portfolio to customers.

In this regard, Johanna Swan also said in an interview with Semiconductor Industry Observer: "It is certain that Intel's foundry customers will be able to use the cutting-edge packaging technologies that we are ready to deploy, including 2D, 2.5D or 3D technologies."

According to Johanna Swan, after entering the IDM 2.0 era, Intel will continue to develop advanced packaging technologies such as 2D, 2.5D and 3D. Intel will also provide these technologies to foundry customers to meet their unique product needs.

From the above responses, we can see that advanced packaging will be the key to differentiating future products. Therefore, the understanding of advanced packaging and the advantages of advanced packaging that are different from other foundry manufacturers may be the key to whether its advanced packaging technology can be accepted by the larger market.

Intel believes that the improvement in power efficiency, interconnection density and scalability is the guiding light for the development of Intel's advanced packaging. Based on this, Intel also presented its packaging technology roadmap at its Architecture Day.

As shown in the figure, from standard packaging to EMIB (Embedded Multi-die Interconnect Bridge) and then to Foveros, the bump pitch is reduced from 100μm to 50-25μm. Whether it is EMIB (Embedded Multi-die Interconnect Bridge) or Foveros, these are Intel's past in the field of advanced packaging. For the future, how will they go?

“The opportunity we have is to deliver the most blocks per cubic millimeter and get the most functionality per cubic millimeter,” said Johanna Swan. “But we haven’t reached the limit yet in this regard.”

Based on this understanding, Intel will also work to develop packaging technology with bump pitch less than 10 microns in the future.

In Intel's view, hybrid bonding is one of the key technologies to achieve a bump pitch of less than 10 microns. Hybrid bonding was also the solution first proposed by Intel on its architecture last year. At this year's ECTC, Intel once again announced some details about hybrid bonding. According to Intel, the use of hybrid bonding can also achieve a smaller form factor.

It is reported that Foveros, which has a bump pitch of 50 microns, contains about 400 bumps per square millimeter. But for Hybrid Bonding, which achieves a bump pitch of less than 10 microns, it can accommodate 10,000 bumps per square millimeter. Johanna Swan said: "In this way, we can achieve more interconnections between the two chips, which also means that this method can provide smaller and simpler circuits because they can actually be superimposed on each other. Therefore, there is no need to do fan-in and fan-out. With this simpler circuit, we can use lower capacitance. Then start to reduce the power of this channel."

At the same time, Johanna Swan also pointed out that due to the differences in assembly processes between Foveros and Hybrid Bonding, a new manufacturing, cleaning and testing method is required when using Hybrid Bonding.

The original intention of using Hybrid Bonding is to integrate more IPs or tiles together and realize chip-to-chip interconnection. This means that when switching from welding to Hybrid Bonding, the manufacturing process must be kept at the same speed and more IPs or chips must be placed together.

To solve this challenge, Intel is considering the solution of batch assembly, which they call self-assembly. According to reports, Intel is working with CEA-LETI to promote hybrid bonding self-assembly research.

Johanna Swan said that the technological advances in hybrid bonding can also be used for CO-EMIB and ODI architectures, which are technologies launched by Intel Advanced Packaging in terms of scalability.

From this, we can see that Hybrid Bonding can not only help improve power efficiency and interconnection density, but also provide support in scalability. Therefore, the author believes that Hybrid Bonding will become the key to the development of Intel's advanced packaging.

The market is an important factor driving the upgrade of packaging technology.

"Providing unique solutions drives the technology we focus on." Johanna Swan said: "The continuous evolution of product requirements is what really drives the need for packaging changes." She believes that advances in packaging technology will emerge with the differentiated needs of users.

In Johanna Swan's view, customization is the real reason for achieving the next stage of heterogeneous integration. Therefore, the market will need to obtain more different node or IP combinations to perform this operation on different processes or nodes. Through this mix and match, it can be deeply customized for specific customers.

On this basis, Johanna Swan believes that extreme heterogeneous integration is the future trend of packaging technology. She said: "Packaging technology will continue to have the characteristics of shrinking size. As we demonstrated at the Architecture Day, we can package smaller and smaller IP and smaller and smaller tiles together."

Process & packaging is one of the six major technology pillars for Intel's future development. As an important part of this pillar, Intel has also made a series of arrangements for its packaging technology. This includes Intel's announcement in May this year that it will invest $3.5 billion to equip its Rio Rancho plant in New Mexico with advanced packaging equipment, including Foveros technology, and is expected to start construction at the end of 2021.

In addition, Intel has frequently mentioned their recent research and progress in advanced packaging in papers and speeches published at many authoritative semiconductor industry conferences.

From this series of actions, we can see through Intel, an industry giant, that the value of packaging technology is changing.